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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
184 lines
7.4 KiB
Diff
184 lines
7.4 KiB
Diff
From 86e03654997db1b70e71f717ab3e74b1df2f402c Mon Sep 17 00:00:00 2001
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From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Date: Thu, 13 Jul 2017 18:28:27 +0800
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Subject: [PATCH] arm64: dts: freescale: lx2160a: add pcie DT nodes
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The LX2160A integrated 6 PCIe Gen4 controllers.
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Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 162 +++++++++++++++++++++++++
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1 file changed, 162 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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@@ -903,6 +903,168 @@
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status = "disabled";
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};
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+ pcie@3400000 {
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+ compatible = "fsl,lx2160a-pcie";
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+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
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+ reg-names = "csr_axi_slave", "config_axi_slave";
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+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
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+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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+ interrupt-names = "aer", "pme", "intr";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ dma-coherent;
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+ apio-wins = <8>;
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+ ppio-wins = <8>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&its>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ pcie@3500000 {
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+ compatible = "fsl,lx2160a-pcie";
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+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
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+ 0x88 0x00000000 0x0 0x00001000>; /* configuration space */
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+ reg-names = "csr_axi_slave", "config_axi_slave";
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+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
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+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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+ interrupt-names = "aer", "pme", "intr";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ dma-coherent;
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+ apio-wins = <8>;
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+ ppio-wins = <8>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&its>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ pcie@3600000 {
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+ compatible = "fsl,lx2160a-pcie";
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+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
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+ 0x90 0x00000000 0x0 0x00001000>; /* configuration space */
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+ reg-names = "csr_axi_slave", "config_axi_slave";
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+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
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+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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+ interrupt-names = "aer", "pme", "intr";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ dma-coherent;
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+ apio-wins = <8>;
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+ ppio-wins = <8>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&its>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ pcie@3700000 {
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+ compatible = "fsl,lx2160a-pcie";
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+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
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+ 0x98 0x00000000 0x0 0x00001000>; /* configuration space */
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+ reg-names = "csr_axi_slave", "config_axi_slave";
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
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+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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+ interrupt-names = "aer", "pme", "intr";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ dma-coherent;
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+ apio-wins = <8>;
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+ ppio-wins = <8>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&its>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ pcie@3800000 {
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+ compatible = "fsl,lx2160a-pcie";
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+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
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+ 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
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+ reg-names = "csr_axi_slave", "config_axi_slave";
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+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
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+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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+ interrupt-names = "aer", "pme", "intr";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ dma-coherent;
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+ apio-wins = <8>;
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+ ppio-wins = <8>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&its>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ pcie@3900000 {
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+ compatible = "fsl,lx2160a-pcie";
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+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
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+ 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
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+ reg-names = "csr_axi_slave", "config_axi_slave";
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+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
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+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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+ interrupt-names = "aer", "pme", "intr";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ dma-coherent;
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+ apio-wins = <8>;
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+ ppio-wins = <8>;
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+ bus-range = <0x0 0xff>;
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+ ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&its>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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+ <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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smmu: iommu@5000000 {
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compatible = "arm,mmu-500";
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reg = <0 0x5000000 0 0x800000>;
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