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layerscape: add patches-5.4

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Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit is contained in:
Yangbo Lu 2020-04-10 10:47:05 +08:00 committed by Petr Štetiar
parent d1d2c0b557
commit cddd459140
916 changed files with 353650 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
target/linux/layerscape/patches-5.4/301-arch-0001-arm-kernel-utilize-hrtimer-based-broadcast.patch Normal file
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@ -0,0 +1,33 @@
From 0f87c1dd8f10958121e10219c89e8d710babd1ce Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Fri, 17 Jul 2015 17:11:52 +0800
Subject: [PATCH] arm: kernel: utilize hrtimer based broadcast
Hrtimer based broadcast is used on ARM platform. It can be
registered as the tick broadcast device in the absence of
a real external clock device.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
---
arch/arm/kernel/time.c | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -9,6 +9,7 @@
* reading the RTC at bootup, etc...
*/
#include <linux/clk-provider.h>
+#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/errno.h>
#include <linux/export.h>
@@ -107,5 +108,7 @@ void __init time_init(void)
of_clk_init(NULL);
#endif
timer_probe();
+
+ tick_setup_hrtimer_broadcast();
}
}

25
target/linux/layerscape/patches-5.4/301-arch-0002-arm64-add-support-to-remap-kernel-cacheable-memory-t.patch Normal file
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@ -0,0 +1,25 @@
From 0f90f5d6b3097fd6e7dea3389dc3d8f8894b345c Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Wed, 22 Apr 2015 13:09:47 -0400
Subject: [PATCH] arm64: add support to remap kernel cacheable memory to
userspace
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
---
arch/arm64/include/asm/pgtable.h | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -414,6 +414,9 @@ static inline pmd_t pmd_mkdevmap(pmd_t p
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
#define pgprot_writecombine(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
+#define pgprot_cached(prot) \
+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
+ PTE_PXN | PTE_UXN)
#define pgprot_device(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
/*

22
target/linux/layerscape/patches-5.4/301-arch-0003-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch Normal file
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@ -0,0 +1,22 @@
From d59be41c014e2e17ea0aaa37d42f36548ad063b5 Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.wang@freescale.com>
Date: Sat, 8 Aug 2015 07:25:02 -0400
Subject: [PATCH] arm64/pgtable: add support to map cacheable and non shareable
memory
Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
---
arch/arm64/include/asm/pgtable.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -417,6 +417,8 @@ static inline pmd_t pmd_mkdevmap(pmd_t p
#define pgprot_cached(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
PTE_PXN | PTE_UXN)
+#define pgprot_cached_ns(prot) \
+ __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
#define pgprot_device(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
/*

33
target/linux/layerscape/patches-5.4/301-arch-0004-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch Normal file
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@ -0,0 +1,33 @@
From 120c8f221cb18f6630d5cb954484bac88288cced Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Wed, 22 Apr 2015 13:07:25 -0400
Subject: [PATCH] arm64: add ioremap for normal cacheable non-shareable memory
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
---
arch/arm64/include/asm/io.h | 1 +
arch/arm64/include/asm/pgtable-prot.h | 1 +
2 files changed, 2 insertions(+)
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -170,6 +170,7 @@ extern void __iomem *ioremap_cache(phys_
#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
#define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
+#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS))
/*
* PCI configuration space mapping function.
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -37,6 +37,7 @@
#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
+#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))

79
target/linux/layerscape/patches-5.4/301-arch-0005-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch Normal file
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@ -0,0 +1,79 @@
From 3bc37b0ee99b9d66ac47aea02784242cb3224366 Mon Sep 17 00:00:00 2001
From: Zhao Qiang <B45475@freescale.com>
Date: Fri, 10 Oct 2014 10:38:48 +0800
Subject: [PATCH] arch: arm: add ARM specific fucntions required for ehci fsl
driver
Add below functions for ARM platform which are used by ehci fsl driver:
1. spin_event_timeout function
2. set/clear bits functions
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/include/asm/delay.h | 16 ++++++++++++++++
arch/arm/include/asm/io.h | 28 ++++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -85,6 +85,22 @@ extern void __bad_udelay(void);
__const_udelay((n) * UDELAY_MULT)) : \
__udelay(n))
+#define spin_event_timeout(condition, timeout, delay) \
+({ \
+ typeof(condition) __ret; \
+ int i = 0; \
+ while (!(__ret = (condition)) && (i++ < timeout)) { \
+ if (delay) \
+ udelay(delay); \
+ else \
+ cpu_relax(); \
+ udelay(1); \
+ } \
+ if (!__ret) \
+ __ret = (condition); \
+ __ret; \
+})
+
/* Loop-based definitions for assembly code. */
extern void __loop_delay(unsigned long loops);
extern void __loop_udelay(unsigned long usecs);
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -224,6 +224,34 @@ void __iomem *pci_remap_cfgspace(resourc
#endif
#endif
+/* access ports */
+#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
+#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
+
+#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
+#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
+
+#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
+#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
+
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single read-modify-write. These
+ * macros can also be used to set a multiple-bit bit pattern using a mask,
+ * by specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrsetbits_be32(addr, clear, set) \
+ iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_le32(addr, clear, set) \
+ iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_be16(addr, clear, set) \
+ iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_le16(addr, clear, set) \
+ iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_8(addr, clear, set) \
+ iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
+
/*
* IO port access primitives
* -------------------------

17
target/linux/layerscape/patches-5.4/301-arch-0006-export-arch_setup_dma_ops.patch Normal file
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@ -0,0 +1,17 @@
From 1c86c2f332b3aafb119c4d1ef981cd2a44286a81 Mon Sep 17 00:00:00 2001
From: Madalin Bucur <madalin.bucur@nxp.com>
Date: Wed, 7 Jun 2017 17:54:10 +0300
Subject: [PATCH] export arch_setup_dma_ops()
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
---
arch/arm64/mm/dma-mapping.c | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -57,3 +57,4 @@ void arch_setup_dma_ops(struct device *d
dev->dma_ops = &xen_swiotlb_dma_ops;
#endif
}
+EXPORT_SYMBOL(arch_setup_dma_ops);

23
target/linux/layerscape/patches-5.4/301-arch-0007-arm-dma-mapping-export-arch_setup_dma_ops.patch Normal file
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@ -0,0 +1,23 @@
From 5f1b16ecaac2e891c43a9bbce0f5ee1c18e5aba7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
Date: Mon, 19 Jun 2017 16:38:59 +0300
Subject: [PATCH] arm: dma-mapping: export arch_setup_dma_ops()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
arch/arm/mm/dma-mapping.c | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -2320,6 +2320,7 @@ void arch_setup_dma_ops(struct device *d
#endif
dev->archdata.dma_ops_setup = true;
}
+EXPORT_SYMBOL(arch_setup_dma_ops);
void arch_teardown_dma_ops(struct device *dev)
{

95
target/linux/layerscape/patches-5.4/301-arch-0008-arm-add-new-non-shareable-ioremap.patch Normal file
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@ -0,0 +1,95 @@
From e5bf75ca33946d81c82014168042a64db7c81551 Mon Sep 17 00:00:00 2001
From: Pan Jiafei <Jiafei.Pan@nxp.com>
Date: Thu, 17 Mar 2016 02:01:03 +0000
Subject: [PATCH] arm: add new non-shareable ioremap
Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
---
arch/arm/include/asm/io.h | 3 +++
arch/arm/include/asm/mach/map.h | 4 ++--
arch/arm/mm/ioremap.c | 7 +++++++
arch/arm/mm/mmu.c | 9 +++++++++
4 files changed, 21 insertions(+), 2 deletions(-)
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -123,6 +123,7 @@ static inline u32 __raw_readl(const vola
#define MT_DEVICE_NONSHARED 1
#define MT_DEVICE_CACHED 2
#define MT_DEVICE_WC 3
+#define MT_MEMORY_RW_NS 4
/*
* types 4 onwards can be found in asm/mach/map.h and are undefined
* for ioremap
@@ -438,6 +439,8 @@ void __iomem *ioremap_wc(resource_size_t
#define ioremap_wc ioremap_wc
#define ioremap_wt ioremap_wc
+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size);
+
void iounmap(volatile void __iomem *iomem_cookie);
#define iounmap iounmap
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -18,9 +18,9 @@ struct map_desc {
unsigned int type;
};
-/* types 0-3 are defined in asm/io.h */
+/* types 0-4 are defined in asm/io.h */
enum {
- MT_UNCACHED = 4,
+ MT_UNCACHED = 5,
MT_CACHECLEAN,
MT_MINICLEAN,
MT_LOW_VECTORS,
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -399,6 +399,13 @@ void __iomem *ioremap_wc(resource_size_t
}
EXPORT_SYMBOL(ioremap_wc);
+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size)
+{
+ return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS,
+ __builtin_return_address(0));
+}
+EXPORT_SYMBOL(ioremap_cache_ns);
+
/*
* Remap an arbitrary physical address space into the kernel virtual
* address space as memory. Needed when the kernel wants to execute
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -312,6 +312,13 @@ static struct mem_type mem_types[] __ro_
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
.domain = DOMAIN_KERNEL,
},
+ [MT_MEMORY_RW_NS] = {
+ .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+ L_PTE_XN,
+ .prot_l1 = PMD_TYPE_TABLE,
+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN,
+ .domain = DOMAIN_KERNEL,
+ },
[MT_ROM] = {
.prot_sect = PMD_TYPE_SECT,
.domain = DOMAIN_KERNEL,
@@ -648,6 +655,7 @@ static void __init build_mem_type_table(
}
kern_pgprot |= PTE_EXT_AF;
vecs_pgprot |= PTE_EXT_AF;
+ mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte;
/*
* Set PXN for user mappings
@@ -676,6 +684,7 @@ static void __init build_mem_type_table(
mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
+ mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd;
mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
mem_types[MT_ROM].prot_sect |= cp->pmd;

26
target/linux/layerscape/patches-5.4/301-arch-0009-arm-add-pgprot_cached-and-pgprot_cached_ns-support.patch Normal file
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@ -0,0 +1,26 @@
From 395718e9f6445369089dba16fa50182c5e0528f5 Mon Sep 17 00:00:00 2001
From: Jianhua Xie <jianhua.xie@nxp.com>
Date: Fri, 29 Jan 2016 16:40:46 +0800
Subject: [PATCH] arm: add pgprot_cached and pgprot_cached_ns support
Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
---
arch/arm/include/asm/pgtable.h | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -116,6 +116,13 @@ extern pgprot_t pgprot_s2_device;
#define pgprot_noncached(prot) \
__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
+#define pgprot_cached(prot) \
+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
+
+#define pgprot_cached_ns(prot) \
+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
+ L_PTE_MT_DEV_NONSHARED)
+
#define pgprot_writecombine(prot) \
__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)

20
target/linux/layerscape/patches-5.4/301-arch-0010-arm64-add-stage-2-cache-able-non-shareable-page-type.patch Normal file
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@ -0,0 +1,20 @@
From 73b06aca47caafdce7bff2c7b27a070d5a8d8172 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Tue, 5 Dec 2017 15:24:05 +0200
Subject: [PATCH] arm64: add stage-2 cache-able non-shareable page type
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/include/asm/pgtable-prot.h | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -78,6 +78,7 @@
})
#define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN)
+#define PAGE_S2_NS __pgprot(PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF)
#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)
#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)

152
target/linux/layerscape/patches-5.4/301-arch-0011-drivers-soc-fsl-add-qixis-driver.patch Normal file
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@ -0,0 +1,152 @@
From 68e332146b6f0a1d2a4514810986a7cf3c3117e3 Mon Sep 17 00:00:00 2001
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Thu, 28 Feb 2019 17:22:28 +0530
Subject: [PATCH] drivers: soc: fsl: add qixis driver
FPGA on LX2160AQDS/LX2160ARDB connected on I2C bus, so add qixis driver
which is basically an i2c client driver to control FPGA.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
drivers/soc/fsl/Kconfig | 11 +++++
drivers/soc/fsl/Makefile | 1 +
drivers/soc/fsl/qixis_ctrl.c | 105 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 117 insertions(+)
create mode 100644 drivers/soc/fsl/qixis_ctrl.c
--- a/drivers/soc/fsl/Kconfig
+++ b/drivers/soc/fsl/Kconfig
@@ -40,4 +40,15 @@ config DPAA2_CONSOLE
/dev/dpaa2_mc_console and /dev/dpaa2_aiop_console,
which can be used to dump the Management Complex and AIOP
firmware logs.
+
+config FSL_QIXIS
+ tristate "QIXIS system controller driver"
+ depends on OF
+ select REGMAP_I2C
+ select REGMAP_MMIO
+ default n
+ help
+ Say y here to enable QIXIS system controller api. The qixis driver
+ provides FPGA functions to control system.
+
endmenu
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_FSL_DPAA) += qbman/
obj-$(CONFIG_QUICC_ENGINE) += qe/
obj-$(CONFIG_CPM) += qe/
+obj-$(CONFIG_FSL_QIXIS) += qixis_ctrl.o
obj-$(CONFIG_FSL_GUTS) += guts.o
obj-$(CONFIG_FSL_MC_DPIO) += dpio/
obj-$(CONFIG_DPAA2_CONSOLE) += dpaa2-console.o
--- /dev/null
+++ b/drivers/soc/fsl/qixis_ctrl.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/* Freescale QIXIS system controller driver.
+ *
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2018-2019 NXP
+ */
+
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/mfd/core.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+/* QIXIS MAP */
+struct fsl_qixis_regs {
+ u8 id; /* Identification Registers */
+ u8 version; /* Version Register */
+ u8 qixis_ver; /* QIXIS Version Register */
+ u8 reserved1[0x1f];
+};
+
+struct qixis_priv {
+ struct regmap *regmap;
+};
+
+static struct regmap_config qixis_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+};
+
+static const struct mfd_cell fsl_qixis_devs[] = {
+ {
+ .name = "reg-mux",
+ .of_compatible = "reg-mux",
+ },
+};
+
+static int fsl_qixis_i2c_probe(struct i2c_client *client)
+{
+ struct qixis_priv *priv;
+ int ret = 0;
+ u32 qver;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+ return -EOPNOTSUPP;
+
+ priv = devm_kzalloc(&client->dev, sizeof(struct qixis_priv),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->regmap = regmap_init_i2c(client, &qixis_regmap_config);
+ regmap_read(priv->regmap, offsetof(struct fsl_qixis_regs, qixis_ver),
+ &qver);
+ pr_info("Freescale QIXIS Version: 0x%08x\n", qver);
+
+ i2c_set_clientdata(client, priv);
+
+ if (of_device_is_compatible(client->dev.of_node, "simple-mfd"))
+ ret = devm_mfd_add_devices(&client->dev, -1, fsl_qixis_devs,
+ ARRAY_SIZE(fsl_qixis_devs), NULL, 0,
+ NULL);
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ regmap_exit(priv->regmap);
+
+ return ret;
+}
+
+static int fsl_qixis_i2c_remove(struct i2c_client *client)
+{
+ struct qixis_priv *priv;
+
+ priv = i2c_get_clientdata(client);
+ regmap_exit(priv->regmap);
+
+ return 0;
+}
+
+static const struct of_device_id fsl_qixis_i2c_of_match[] = {
+ { .compatible = "fsl,fpga-qixis-i2c" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, fsl_qixis_i2c_of_match);
+
+static struct i2c_driver fsl_qixis_i2c_driver = {
+ .driver = {
+ .name = "qixis_ctrl_i2c",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(fsl_qixis_i2c_of_match),
+ },
+ .probe_new = fsl_qixis_i2c_probe,
+ .remove = fsl_qixis_i2c_remove,
+};
+module_i2c_driver(fsl_qixis_i2c_driver);
+
+MODULE_AUTHOR("Wang Dongsheng <dongsheng.wang@freescale.com>");
+MODULE_DESCRIPTION("Freescale QIXIS system controller driver");
+MODULE_LICENSE("GPL");
+

22
target/linux/layerscape/patches-5.4/301-arch-0012-soc-fsl-select-MFD_CORE-for-qixis-driver.patch Normal file
View File

@ -0,0 +1,22 @@
From 5451ebbfc7e8ba51bceb12ee5409364000e6475b Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Thu, 9 Apr 2020 18:24:07 +0800
Subject: [PATCH] soc: fsl: select MFD_CORE for qixis driver
The QIXIS driver should select MFD_CORE option.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/soc/fsl/Kconfig | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/soc/fsl/Kconfig
+++ b/drivers/soc/fsl/Kconfig
@@ -46,6 +46,7 @@ config FSL_QIXIS
depends on OF
select REGMAP_I2C
select REGMAP_MMIO
+ select MFD_CORE
default n
help
Say y here to enable QIXIS system controller api. The qixis driver

550
target/linux/layerscape/patches-5.4/302-dts-0001-sdk-arm64-dts-add-update-DPAA1-include-files-for-SDK.patch Normal file
View File

@ -0,0 +1,550 @@
From fd5901a48f68c74f074ea5c490377b7c9f3899f5 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Fri, 5 Oct 2018 17:52:23 -0500
Subject: [PATCH] sdk: arm64: dts: add/update DPAA1 include files for SDK
flavor
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../boot/dts/freescale/qoriq-bman-portals-sdk.dtsi | 55 +++++++++++++++++
arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 72 ++++++++++++++++++++++
.../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 9 +--
.../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 9 +--
.../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 5 +-
.../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 5 +-
.../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 5 +-
.../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 5 +-
.../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 5 +-
.../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 5 +-
.../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++++++++++++++
arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 52 +++++++++++++++-
.../boot/dts/freescale/qoriq-qman-portals-sdk.dtsi | 38 ++++++++++++
13 files changed, 291 insertions(+), 21 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
@@ -0,0 +1,55 @@
+/*
+ * QorIQ BMan SDK Portals device tree nodes
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&bportals {
+ bman-portal@0 {
+ cell-index = <0>;
+ };
+
+ bman-portal@10000 {
+ cell-index = <1>;
+ };
+
+ bman-portal@20000 {
+ cell-index = <2>;
+ };
+
+ bman-portal@30000 {
+ cell-index = <3>;
+ };
+
+ bman-portal@40000 {
+ cell-index = <4>;
+ };
+
+ bman-portal@50000 {
+ cell-index = <5>;
+ };
+
+ bman-portal@60000 {
+ cell-index = <6>;
+ };
+
+ bman-portal@70000 {
+ cell-index = <7>;
+ };
+
+ bman-portal@80000 {
+ cell-index = <8>;
+ };
+
+ bman-portal@90000 {
+ cell-index = <9>;
+ };
+
+ bman-bpids@0 {
+ compatible = "fsl,bpid-range";
+ fsl,bpid-range = <32 32>;
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
@@ -0,0 +1,72 @@
+/*
+ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+fsldpaa: fsl,dpaa {
+ compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
+ ethernet@0 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet0>;
+ dma-coherent;
+ };
+ ethernet@1 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet1>;
+ dma-coherent;
+ };
+ ethernet@2 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet2>;
+ dma-coherent;
+ };
+ ethernet@3 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet3>;
+ dma-coherent;
+ };
+ ethernet@4 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet4>;
+ dma-coherent;
+ };
+ ethernet@5 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet5>;
+ dma-coherent;
+ };
+ ethernet@8 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet6>;
+ dma-coherent;
+ };
+};
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
@@ -9,19 +9,20 @@
fman@1a00000 {
fman0_rx_0x10: port@90000 {
cell-index = <0x10>;
- compatible = "fsl,fman-v3-port-rx";
+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
reg = <0x90000 0x1000>;
fsl,fman-10g-port;
};
fman0_tx_0x30: port@b0000 {
cell-index = <0x30>;
- compatible = "fsl,fman-v3-port-tx";
+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
reg = <0xb0000 0x1000>;
fsl,fman-10g-port;
+ fsl,qman-channel-id = <0x800>;
};
- ethernet@f0000 {
+ mac9: ethernet@f0000 {
cell-index = <0x8>;
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
@@ -29,7 +30,7 @@ fman@1a00000 {
pcsphy-handle = <&pcsphy6>;
};
- mdio@f1000 {
+ mdio9: mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
@@ -9,19 +9,20 @@
fman@1a00000 {
fman0_rx_0x11: port@91000 {
cell-index = <0x11>;
- compatible = "fsl,fman-v3-port-rx";
+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
reg = <0x91000 0x1000>;
fsl,fman-10g-port;
};
fman0_tx_0x31: port@b1000 {
cell-index = <0x31>;
- compatible = "fsl,fman-v3-port-tx";
+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
reg = <0xb1000 0x1000>;
fsl,fman-10g-port;
+ fsl,qman-channel-id = <0x801>;
};
- ethernet@f2000 {
+ mac10: ethernet@f2000 {
cell-index = <0x9>;
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
@@ -29,7 +30,7 @@ fman@1a00000 {
pcsphy-handle = <&pcsphy7>;
};
- mdio@f3000 {
+ mdio10: mdio@f3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
@@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x08: port@88000 {
cell-index = <0x8>;
- compatible = "fsl,fman-v3-port-rx";
+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x88000 0x1000>;
};
fman0_tx_0x28: port@a8000 {
cell-index = <0x28>;
- compatible = "fsl,fman-v3-port-tx";
+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xa8000 0x1000>;
+ fsl,qman-channel-id = <0x802>;
};
ethernet@e0000 {
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
@@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x09: port@89000 {
cell-index = <0x9>;
- compatible = "fsl,fman-v3-port-rx";
+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x89000 0x1000>;
};
fman0_tx_0x29: port@a9000 {
cell-index = <0x29>;
- compatible = "fsl,fman-v3-port-tx";
+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xa9000 0x1000>;
+ fsl,qman-channel-id = <0x803>;
};
ethernet@e2000 {
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
@@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x0a: port@8a000 {
cell-index = <0xa>;
- compatible = "fsl,fman-v3-port-rx";
+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x8a000 0x1000>;
};
fman0_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
- compatible = "fsl,fman-v3-port-tx";
+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xaa000 0x1000>;
+ fsl,qman-channel-id = <0x804>;
};
ethernet@e4000 {
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
@@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x0b: port@8b000 {
cell-index = <0xb>;
- compatible = "fsl,fman-v3-port-rx";
+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x8b000 0x1000>;
};
fman0_tx_0x2b: port@ab000 {
cell-index = <0x2b>;
- compatible = "fsl,fman-v3-port-tx";
+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xab000 0x1000>;
+ fsl,qman-channel-id = <0x805>;
};
ethernet@e6000 {
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
@@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x0c: port@8c000 {
cell-index = <0xc>;
- compatible = "fsl,fman-v3-port-rx";
+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x8c000 0x1000>;
};
fman0_tx_0x2c: port@ac000 {
cell-index = <0x2c>;
- compatible = "fsl,fman-v3-port-tx";
+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xac000 0x1000>;
+ fsl,qman-channel-id = <0x806>;
};
ethernet@e8000 {
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
@@ -9,14 +9,15 @@
fman@1a00000 {
fman0_rx_0x0d: port@8d000 {
cell-index = <0xd>;
- compatible = "fsl,fman-v3-port-rx";
+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
reg = <0x8d000 0x1000>;
};
fman0_tx_0x2d: port@ad000 {
cell-index = <0x2d>;
- compatible = "fsl,fman-v3-port-tx";
+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
reg = <0xad000 0x1000>;
+ fsl,qman-channel-id = <0x807>;
};
ethernet@ea000 {
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
@@ -0,0 +1,47 @@
+/*
+ * QorIQ FMan v3 OH ports device tree
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+fman@1a00000 {
+
+ fman0_oh1: port@82000 {
+ cell-index = <0>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x82000 0x1000>;
+ };
+
+ fman0_oh2: port@83000 {
+ cell-index = <1>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x83000 0x1000>;
+ };
+
+ fman0_oh3: port@84000 {
+ cell-index = <2>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x84000 0x1000>;
+ };
+
+ fman0_oh4: port@85000 {
+ cell-index = <3>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x85000 0x1000>;
+ };
+
+ fman0_oh5: port@86000 {
+ cell-index = <4>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x86000 0x1000>;
+ };
+
+ fman0_oh6: port@87000 {
+ cell-index = <5>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x87000 0x1000>;
+ };
+
+};
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
@@ -20,45 +20,95 @@ fman0: fman@1a00000 {
fsl,qman-channel-range = <0x800 0x10>;
ptimer-handle = <&ptp_timer0>;
+ cc {
+ compatible = "fsl,fman-cc";
+ };
+
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x60000>;
};
+ bmi@80000 {
+ compatible = "fsl,fman-bmi";
+ reg = <0x80000 0x400>;
+ };
+
+ qmi@80400 {
+ compatible = "fsl,fman-qmi";
+ reg = <0x80400 0x400>;
+ };
+
fman0_oh_0x2: port@82000 {
cell-index = <0x2>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x82000 0x1000>;
+ fsl,qman-channel-id = <0x809>;
};
fman0_oh_0x3: port@83000 {
cell-index = <0x3>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x83000 0x1000>;
+ fsl,qman-channel-id = <0x80a>;
};
fman0_oh_0x4: port@84000 {
cell-index = <0x4>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x84000 0x1000>;
+ fsl,qman-channel-id = <0x80b>;
};
fman0_oh_0x5: port@85000 {
cell-index = <0x5>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x85000 0x1000>;
+ fsl,qman-channel-id = <0x80c>;
};
fman0_oh_0x6: port@86000 {
cell-index = <0x6>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x86000 0x1000>;
+ fsl,qman-channel-id = <0x80d>;
};
fman0_oh_0x7: port@87000 {
cell-index = <0x7>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x87000 0x1000>;
+ fsl,qman-channel-id = <0x80e>;
+ };
+
+ policer@c0000 {
+ compatible = "fsl,fman-policer";
+ reg = <0xc0000 0x1000>;
+ };
+
+ keygen@c1000 {
+ compatible = "fsl,fman-keygen";
+ reg = <0xc1000 0x1000>;
+ };
+
+ dma@c2000 {
+ compatible = "fsl,fman-dma";
+ reg = <0xc2000 0x1000>;
+ };
+
+ fpm@c3000 {
+ compatible = "fsl,fman-fpm";
+ reg = <0xc3000 0x1000>;
+ };
+
+ parser@c7000 {
+ compatible = "fsl,fman-parser";
+ reg = <0xc7000 0x1000>;
+ };
+
+ vsps@dc000 {
+ compatible = "fsl,fman-vsps";
+ reg = <0xdc000 0x1000>;
};
mdio0: mdio@fc000 {
@@ -77,7 +127,7 @@ fman0: fman@1a00000 {
};
ptp_timer0: ptp-timer@1afe000 {
- compatible = "fsl,fman-ptp-timer";
+ compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
reg = <0x0 0x1afe000 0x0 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 3 0>;
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
@@ -0,0 +1,38 @@
+/*
+ * QorIQ QMan SDK Portals device tree nodes
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&qportals {
+ qman-fqids@0 {
+ compatible = "fsl,fqid-range";
+ fsl,fqid-range = <256 256>;
+ };
+
+ qman-fqids@1 {
+ compatible = "fsl,fqid-range";
+ fsl,fqid-range = <32768 32768>;
+ };
+
+ qman-pools@0 {
+ compatible = "fsl,pool-channel-range";
+ fsl,pool-channel-range = <0x401 0xf>;
+ };
+
+ qman-cgrids@0 {
+ compatible = "fsl,cgrid-range";
+ fsl,cgrid-range = <0 256>;
+ };
+
+ qman-ceetm@0 {
+ compatible = "fsl,qman-ceetm";
+ fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
+ fsl,ceetm-sp-range = <0 16>;
+ fsl,ceetm-lni-range = <0 8>;
+ fsl,ceetm-channel-range = <0 32>;
+ };
+};

626
target/linux/layerscape/patches-5.4/302-dts-0002-sdk-arm64-dts-add-DPAA1-SDK-flavor-dts-files.patch Normal file
View File

@ -0,0 +1,626 @@
From 7f3b260e937238632e523306089e856d0db1a4f9 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Fri, 5 Oct 2018 18:03:25 -0500
Subject: [PATCH] sdk: arm64: dts: add DPAA1 SDK flavor dts files
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 6 ++
.../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 71 +++++++++++++
.../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 71 +++++++++++++
.../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++++++++++++++++++++
.../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 79 ++++++++++++++
.../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 115 ++++++++++++++++++++
.../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++++++++++++++++++
7 files changed, 569 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -7,10 +7,16 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
@@ -0,0 +1,71 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "fsl-ls1043a-qds.dts"
+#include "qoriq-qman-portals-sdk.dtsi"
+#include "qoriq-bman-portals-sdk.dtsi"
+
+&bman_fbpr {
+ compatible = "fsl,bman-fbpr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&soc {
+#include "qoriq-dpaa-eth.dtsi"
+#include "qoriq-fman3-0-6oh.dtsi"
+};
+
+&fman0 {
+ compatible = "fsl,fman", "simple-bus";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
@@ -0,0 +1,71 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "fsl-ls1043a-rdb.dts"
+#include "qoriq-qman-portals-sdk.dtsi"
+#include "qoriq-bman-portals-sdk.dtsi"
+
+&bman_fbpr {
+ compatible = "fsl,bman-fbpr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&soc {
+#include "qoriq-dpaa-eth.dtsi"
+#include "qoriq-fman3-0-6oh.dtsi"
+};
+
+&fman0 {
+ compatible = "fsl,fman", "simple-bus";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
@@ -0,0 +1,117 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2014-2015, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "fsl-ls1043a-rdb-sdk.dts"
+
+&soc {
+ bp7: buffer-pool@7 {
+ compatible = "fsl,p4080-bpool", "fsl,bpool";
+ fsl,bpid = <7>;
+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
+ };
+
+ bp8: buffer-pool@8 {
+ compatible = "fsl,p4080-bpool", "fsl,bpool";
+ fsl,bpid = <8>;
+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ };
+
+ bp9: buffer-pool@9 {
+ compatible = "fsl,p4080-bpool", "fsl,bpool";
+ fsl,bpid = <9>;
+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ };
+
+ fsl,dpaa {
+ compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
+
+ ethernet@0 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
+ fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
+ };
+
+ ethernet@1 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
+ fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
+ };
+
+ ethernet@2 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
+ };
+
+ ethernet@3 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
+ };
+
+ ethernet@4 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
+ };
+
+ ethernet@5 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
+ fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
+ };
+
+ ethernet@8 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
+
+ };
+ dpa-fman0-oh@2 {
+ compatible = "fsl,dpa-oh";
+ /* Define frame queues for the OH port*/
+ /* <OH Rx error, OH Rx default> */
+ fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
+ fsl,fman-oh-port = <&fman0_oh2>;
+ };
+ };
+};
+/ {
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ usdpaa_mem: usdpaa_mem {
+ compatible = "fsl,usdpaa-mem";
+ alloc-ranges = <0 0 0x10000 0>;
+ size = <0 0x10000000>;
+ alignment = <0 0x10000000>;
+ };
+ };
+};
+
+&fman0 {
+ fman0_oh2: port@83000 {
+ cell-index = <1>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x83000 0x1000>;
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
@@ -0,0 +1,79 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "fsl-ls1046a-qds.dts"
+#include "qoriq-qman-portals-sdk.dtsi"
+#include "qoriq-bman-portals-sdk.dtsi"
+
+&bman_fbpr {
+ compatible = "fsl,bman-fbpr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&soc {
+#include "qoriq-dpaa-eth.dtsi"
+#include "qoriq-fman3-0-6oh.dtsi"
+};
+
+&fsldpaa {
+ ethernet@9 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet7>;
+ dma-coherent;
+ };
+};
+
+&fman0 {
+ compatible = "fsl,fman", "simple-bus";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
@@ -0,0 +1,115 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "fsl-ls1046a-rdb.dts"
+#include "qoriq-qman-portals-sdk.dtsi"
+#include "qoriq-bman-portals-sdk.dtsi"
+
+&bman_fbpr {
+ compatible = "fsl,bman-fbpr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&soc {
+#include "qoriq-dpaa-eth.dtsi"
+#include "qoriq-fman3-0-6oh.dtsi"
+};
+
+&fsldpaa {
+ ethernet@0 {
+ status = "disabled";
+ };
+ ethernet@1 {
+ status = "disabled";
+ };
+ ethernet@9 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet7>;
+ dma-coherent;
+ };
+};
+
+&fman0 {
+ compatible = "fsl,fman", "simple-bus";
+};
+
+&mdio9 {
+ pcsphy6: ethernet-phy@0 {
+ backplane-mode = "10gbase-kr";
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0x8C0 0x40>; /* lane D */
+ };
+};
+
+&mdio10 {
+ pcsphy7: ethernet-phy@0 {
+ backplane-mode = "10gbase-kr";
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0x880 0x40>; /* lane C */
+ };
+};
+
+/* Update MAC connections to backplane PHYs
+ * &mac9 {
+ * phy-handle = <&pcsphy6>;
+ *};
+ *
+ *&mac10 {
+ * phy-handle = <&pcsphy7>;
+ *};
+*/
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
@@ -0,0 +1,110 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "fsl-ls1046a-rdb-sdk.dts"
+
+&soc {
+ bp7: buffer-pool@7 {
+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
+ fsl,bpid = <7>;
+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
+ };
+
+ bp8: buffer-pool@8 {
+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
+ fsl,bpid = <8>;
+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ };
+
+ bp9: buffer-pool@9 {
+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
+ fsl,bpid = <9>;
+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ };
+
+ fsl,dpaa {
+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
+
+ ethernet@2 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
+ };
+
+ ethernet@3 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
+ };
+
+ ethernet@4 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
+ };
+
+ ethernet@5 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
+ fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
+ };
+
+ ethernet@8 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
+ };
+
+ ethernet@9 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
+ fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
+ };
+
+ dpa-fman0-oh@2 {
+ compatible = "fsl,dpa-oh";
+ /* Define frame queues for the OH port*/
+ /* <OH Rx error, OH Rx default> */
+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
+ fsl,fman-oh-port = <&fman0_oh2>;
+ };
+ };
+};
+/ {
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ usdpaa_mem: usdpaa_mem {
+ compatible = "fsl,usdpaa-mem";
+ alloc-ranges = <0 0 0x10000 0>;
+ size = <0 0x10000000>;
+ alignment = <0 0x10000000>;
+ };
+ };
+};
+
+&fman0 {
+ fman0_oh2: port@83000 {
+ cell-index = <1>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x83000 0x1000>;
+ };
+};

114
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@ -0,0 +1,114 @@
From 3261cabf5607c9f434faa4930ab5c2b0150579c4 Mon Sep 17 00:00:00 2001
From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Wed, 29 Nov 2017 06:23:14 +0530
Subject: [PATCH] arm64: dts: ls1012a: Add LS1012A-2G5RDB board support
LS1012A-2G5RDB is a different design from LS1012ARDB,
but has some common SoC features. Key feature on this
board is 2.5Gbps SGMII.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 86 ++++++++++++++++++++++
2 files changed, 87 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for NXP LS1012A 2G5RDB Board.
+ *
+ * Copyright 2017 NXP
+ *
+ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A 2G5RDB Board";
+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&qspi {
+ num-cs = <2>;
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+ reg = <0>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
+
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii-2500";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = < 0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii-2500";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};

149
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@ -0,0 +1,149 @@
From 9ba5a56b7241c46aa47544f8414ad1f3d445f3c1 Mon Sep 17 00:00:00 2001
From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Mon, 7 May 2018 11:52:04 +0530
Subject: [PATCH] arm64: dts: ls1012a: Add more nodes to LS1012A-FRWY board
support
LS1012A-FRWY is a different design from LS1012A-FRDM,
but has some common SoC features. Key feature on this
board is 2x1G SGMII PFE MAC, Micro SD, USB 3.0, DDR,
QuadSPI, Audio, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 118 +++++++++++++++++++++
1 file changed, 118 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
@@ -14,6 +14,58 @@
/ {
model = "LS1012A FRWY Board";
compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
+
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ system-clock-frequency = <25000000>;
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
};
&duart0 {
@@ -22,4 +74,70 @@
&i2c0 {
status = "okay";
+
+ codec: sgtl5000@a {
+ compatible = "fsl,sgtl5000";
+ #sound-dai-cells = <0>;
+ reg = <0xa>;
+ VDDA-supply = <&reg_1p8v>;
+ VDDIO-supply = <&reg_1p8v>;
+ clocks = <&sys_mclk>;
+ };
+};
+
+&qspi {
+ num-cs = <1>;
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: w25q16dw@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
+&sai2 {
+ status = "okay";
};

164
target/linux/layerscape/patches-5.4/302-dts-0005-arm64-dts-ls2081ardb-Add-DTS-support-for-NXP-LS2081A.patch Normal file
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@ -0,0 +1,164 @@
From 5508bc9764760ca32990d5f7fa494be78e711ff6 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Fri, 5 Oct 2018 18:22:46 -0500
Subject: [PATCH] arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDB
This patch add support for NXP LS2081ARDB board which has
LS2081A SoC.
LS2081A SoC is 40-pin derivative of LS2088A SoC
So, from functional perspective both are same.
Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Tao Yang <b31903@freescale.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 127 ++++++++++++++++++++++
2 files changed, 128 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for NXP LS2081A RDB Board.
+ *
+ * Copyright 2017 NXP
+ *
+ * Priyanka Jain <priyanka.jain@nxp.com>
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2088a.dtsi"
+
+/ {
+ model = "NXP Layerscape 2081A RDB Board";
+ compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+};
+
+&esdhc {
+ status = "okay";
+};
+
+&ifc {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547@75 {
+ compatible = "nxp,pca9547";
+ reg = <0x75>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x01>;
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x02>;
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <500>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ adt7481@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&dspi {
+ status = "okay";
+ dflash0: n25q512a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80";
+ spi-max-frequency = <3000000>;
+ reg = <0>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ fsl,qspi-has-second-chip;
+ flash0: s25fs512s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80";
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+ flash1: s25fs512s@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ compatible = "spansion,m25p80";
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};

461
target/linux/layerscape/patches-5.4/302-dts-0006-arm64-dts-ls1012a-accumulated-change-for-ls1012a-boa.patch Normal file
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@ -0,0 +1,461 @@
From 8fd1ab38e922383fa87db60c48c44ab0d5e6f1c1 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Thu, 2 May 2019 15:52:49 -0500
Subject: [PATCH] arm64: dts: ls1012a: accumulated change for ls1012a boards
commit 65c558ec270003e8e99cb58c940d3b913d08fa39
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue May 15 08:47:19 2018 +0800
arm64: dts: ls1012a: correct the register range of dcfg
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 8f7b4cded4ea1fca53516ae8f5d5bc89af291f26
Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Mon May 7 11:52:04 2018 +0530
arm64: dts: ls1012a: Add LS1012A-FRWY board support
LS1012A-FRWY is a different design from LS1012A-FRDM,
but has some common SoC features. Key feature on this
board is 2x1G SGMII PFE MAC, Micro SD, USB 3.0, DDR,
QuadSPI, Audio, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
commit 94fc77837b3b6f4213a49b29ddc3e09e38ae5fbb
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:16:47 2018 +0800
arm64: dts: ls1012a: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit d4164a6d8cffd8f09c451073754834d58b7ace19
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Thu Feb 1 23:44:15 2018 +0530
arm64: dts: freescale: ls1012a: Add DT nodes for qspi
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
commit 4fdc98a03492b732a48426a4180f7d6a36847e71
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Wed Nov 1 10:31:47 2017 +0800
arm64: dts: ls1012a: correct the i2c clock to 1/4 platform pll
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit bb534725996b92aff853a4dee43738629fd4ac08
Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Date: Wed Nov 29 06:31:23 2017 +0530
arm64: dts: freescale: ls1012a: Disable PCIe node as default
Keep PCIe node in "disabled" status as SoC default.
Only enable it for boards with PCIe circuit designed,
such as LS1012ARDB and LS1012AQDS.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
commit 6b9a3244baba2c5126f349800ecaad83ba97ee47
Author: Calvin Johnson <calvin.johnson@nxp.com>
Date: Mon Oct 16 12:25:19 2017 +0530
arm64: dts: freescale: ls1012a: fix RGMII tx delay issue
Recently logic to enable RGMII tx delay was changed by
below patch.
https://patchwork.kernel.org/patch/9447581/
Based on the patch, enabling tx delay again using rgmii-txid.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
commit 1e17e247088f6e2c08041559e38053b70a9d2bbe
Author: Calvin Johnson <calvin.johnson@nxp.com>
Date: Sat Sep 16 14:20:23 2017 +0530
arm64: dts: freescale: ls1012a: update with pppfe support
Update ls1012a dtsi and platform dts files with
support for ppfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
commit e9661ed864d2a9d437057f97729410bb9af994f2
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Tue May 16 17:17:21 2017 +0530
arm64: dts: ls1012a: add the DTS node for QSPI support
There is a s25fs512s qspi flash on QDS, RDB and FRDM board.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
commit ed9c51239461fe0322da2e93f50033ea0d05bc4f
Author: Chenhui Zhao <chenhui.zhao@nxp.com>
Date: Fri May 5 17:45:15 2017 +0800
arm64: dts: ls1012a: add ftm0 node
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 58 ++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 62 ++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 62 ++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 68 +++++++++++++++++++++-
4 files changed, 248 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -13,6 +13,11 @@
model = "LS1012A Freedom Board";
compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -74,6 +79,44 @@
};
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
&sai2 {
status = "okay";
};
@@ -81,3 +124,18 @@
&sata {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+ reg = <0>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -13,6 +13,11 @@
model = "LS1012A QDS Board";
compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -57,6 +62,10 @@
};
};
+&pcie {
+ status = "okay";
+};
+
&dspi {
bus-num = <0>;
status = "okay";
@@ -128,6 +137,44 @@
};
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x2>;
+ phy-mode = "sgmii-2500";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x3>;
+ phy-mode = "sgmii-2500";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
&sai2 {
status = "okay";
};
@@ -135,3 +182,18 @@
&sata {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+ reg = <0>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -12,6 +12,15 @@
/ {
model = "LS1012A RDB Board";
compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+};
+
+&pcie {
+ status = "okay";
};
&duart0 {
@@ -38,3 +47,56 @@
&sata {
status = "okay";
};
+
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x1>; /* enabled/disabled */
+ };
+ };
+
+ ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "rgmii-txid";
+ fsl,pfe-phy-if-flags = <0x0>;
+
+ mdio@0 {
+ reg = <0x0>; /* enabled/disabled */
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+ reg = <0>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -260,7 +260,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1012a-dcfg",
"syscon";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
+ reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@@ -317,13 +317,23 @@
#thermal-sensor-cells = <1>;
};
+ ftm0: ftm0@29d0000 {
+ compatible = "fsl,ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x1ee2140 0x0 0x4>;
+ reg-names = "ftm", "FlexTimer1";
+ interrupts = <0 86 0x4>;
+ big-endian;
+ };
+
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
+ scl-gpios = <&gpio0 13 0>;
status = "disabled";
};
@@ -395,6 +405,20 @@
big-endian;
};
+ qspi: spi@1550000 {
+ compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+ <0x0 0x40000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "qspi_en", "qspi";
+ clocks = <&clockgen 4 0>, <&clockgen 4 0>;
+ big-endian;
+ status = "disabled";
+ };
+
sai1: sai@2b50000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
@@ -499,6 +523,46 @@
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ rcpm: rcpm@1ee2000 {
+ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
+ reg = <0x0 0x1ee2000 0x0 0x1000>;
+ fsl,#rcpm-wakeup-cells = <1>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pfe_reserved: packetbuffer@83400000 {
+ reg = <0 0x83400000 0 0xc00000>;
+ };
+ };
+
+ pfe: pfe@04000000 {
+ compatible = "fsl,pfe";
+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
+ reg-names = "pfe", "pfe-ddr";
+ fsl,pfe-num-interfaces = <0x2>;
+ interrupts = <0 172 0x4>, /* HIF interrupt */
+ <0 173 0x4>, /*HIF_NOCPY interrupt */
+ <0 174 0x4>; /* WoL interrupt */
+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
+ memory-region = <&pfe_reserved>;
+ fsl,pfe-scfg = <&scfg 0>;
+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "pfe";
+
+ status = "okay";
+ pfe_mac0: ethernet@0 {
+ };
+
+ pfe_mac1: ethernet@1 {
+ };
};
firmware {

574
target/linux/layerscape/patches-5.4/302-dts-0007-arm64-dts-ls1043a-accumulated-change-for-ls1043a-boa.patch Normal file
View File

@ -0,0 +1,574 @@
From 794b9e55c77bf0ef34dfdb3b151a845c004b3ce3 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Thu, 2 May 2019 16:01:01 -0500
Subject: [PATCH] arm64: dts: ls1043a: accumulated change for ls1043a boards
commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce
Author: Peng Ma <peng.ma@nxp.com>
Date: Wed Jul 25 08:53:07 2018 +0000
dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node
support
add block-offset to support different virtual block offset for qdma
base on soc;
the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual
block,N based on block number of qdma;
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:22:40 2018 +0800
arm64: dts: ls1043a: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit a47e4bd0b5d076feb6d81601c16d5b79e53a92c8
Author: Rajesh Bhagat <rajesh.bhagat@freescale.com>
Date: Wed Jan 27 11:37:25 2016 +0530
arm64: dts: ls1043a: Add configure-gfladj property to USB3 node
Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustent is required
or not
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
Author: Changming Huang <jerry.huang@nxp.com>
Date: Wed Apr 19 12:49:50 2017 +0800
arm/arm64: dts: Add property snps incr burst type adjustment for
INCR burst type for dwc3
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 8632d84e0fe187aa023a24f0dad0040c53e12450
Author: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Date: Thu Jan 25 11:31:13 2018 +0530
arm64: dts: freescale: ls1043a: Modify DT nodes for qspi
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
commit b1dc1ebed79e9aaab75fd06837d794ec2f1b624d
Author: Ran Wang <ran.wang_1@nxp.com>
Date: Fri Jan 5 15:14:48 2018 +0800
arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node
Enable USB3 HW LPM feature for ls1043a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue Jun 13 13:14:26 2017 +0800
arm64: dts: correct the register range of dcfg
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit f60e39fd51ad702e3a2613faaca40871a4763735
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue Aug 22 18:04:02 2017 +0800
arm64: dts: ls1043a: add pcf85263 rtc nodes
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 67c82e3c7b376139d7cee624589bedbc311f8868
Author: jiaheng.fan <jiaheng.fan@nxp.com>
Date: Thu May 11 17:36:33 2017 +0800
arm64: dts: ls1021/ls1043/ls1046: add qdma nodes
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
commit c6d9c2498ee83669f9853100301edff9a5905caf
Author: Wang Dongsheng <dongsheng.wang@nxp.com>
Date: Fri Apr 21 13:26:07 2017 +0800
arm64: dts: ls1043a: add ftm0 nodes
Add rcpm and ftm0 nodes. The Power Management related features
need these nodes.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
Author: Po Liu <po.liu@nxp.com>
Date: Fri Sep 30 17:11:36 2016 +0800
arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
Some platforms(NXP Layerscape for example) aer/pme interrupts was
not
MSI/MSI-X/INTx but using interrupt line independently. This patch
add "aer", "pme" interrupt-names for aer/pme interrupt.
With the interrupt-names "aer", "pme" code could probe aer/pme
interrupt
line for pcie root port, replace the aer/pme interrupt service irqs.
This is intend to fixup the Layerscape platforms which aer/pmes
interrupts
was not MSI/MSI-X/INTx, but using interrupt line independently.
Since the interrupt-names "intr" never been used. Remove it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
commit 4d20ecf029f1255520b30c103e1724c618b981c7
Author: Zhao Qiang <qiang.zhao@nxp.com>
Date: Sun Jun 12 15:51:44 2016 +0800
arm64: dts: ls1043ardb: add ds26522 node
add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
commit ca470562646ab058814fc4a1195016fb3266cdf5
Author: Zhao Qiang <qiang.zhao@nxp.com>
Date: Sun Jun 12 15:44:11 2016 +0800
arm64: dts: ls1043ardb: add qe node
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 162 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 36 +++++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 108 +++++++++++++--
3 files changed, 295 insertions(+), 11 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -24,6 +24,22 @@
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
+ sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
+ sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
+ sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
+ sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
+ qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
+ qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
+ qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
+ qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
+ qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
+ qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
+ qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
+ qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
+ emi1_slot1 = &ls1043mdio_s1;
+ emi1_slot2 = &ls1043mdio_s2;
+ emi1_slot3 = &ls1043mdio_s3;
+ emi1_slot4 = &ls1043mdio_s4;
};
chosen {
@@ -64,6 +80,8 @@
fpga: board-control@2,0 {
compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
};
@@ -149,3 +167,147 @@
};
#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy_s2_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&qsgmii_phy_s2_p2>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&qsgmii_phy_s2_p3>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&qsgmii_phy_s2_p4>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* DTSEC9/10GEC1 */
+ fixed-link = <1 1 10000 0 0>;
+ phy-connection-type = "xgmii";
+ };
+};
+
+&fpga {
+ mdio-mux-emi1 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1 */
+
+ /* On-board RGMII1 PHY */
+ ls1043mdio0: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
+ reg = <0x1>;
+ };
+ };
+
+ /* On-board RGMII2 PHY */
+ ls1043mdio1: mdio@1 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
+ reg = <0x2>;
+ };
+ };
+
+ /* Slot 1 */
+ ls1043mdio_s1: mdio@2 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s1_p1: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+ qsgmii_phy_s1_p2: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+ qsgmii_phy_s1_p3: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+ qsgmii_phy_s1_p4: ethernet-phy@7 {
+ reg = <0x7>;
+ };
+
+ sgmii_phy_s1_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 2 */
+ ls1043mdio_s2: mdio@3 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s2_p1: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+ qsgmii_phy_s2_p2: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+ qsgmii_phy_s2_p3: ethernet-phy@a {
+ reg = <0xa>;
+ };
+ qsgmii_phy_s2_p4: ethernet-phy@b {
+ reg = <0xb>;
+ };
+
+ sgmii_phy_s2_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 3 */
+ ls1043mdio_s3: mdio@4 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s3_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 4 */
+ ls1043mdio_s4: mdio@5 {
+ reg = <0xa0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s4_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ };
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -49,6 +49,10 @@
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
};
&ifc {
@@ -94,6 +98,38 @@
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
+
+ slic@2 {
+ compatible = "maxim,ds26522";
+ reg = <2>;
+ spi-max-frequency = <2000000>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
+
+ slic@3 {
+ compatible = "maxim,ds26522";
+ reg = <3>;
+ spi-max-frequency = <2000000>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
+};
+
+&uqe {
+ ucc_hdlc: ucc@2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot-mask = <0xfffffffe>;
+ fsl,rx-timeslot-mask = <0xfffffffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
};
&duart0 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -277,7 +277,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1043a-dcfg", "syscon";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
+ reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@@ -411,7 +411,7 @@
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@@ -421,6 +421,7 @@
dmas = <&edma0 1 39>,
<&edma0 1 38>;
dma-names = "tx", "rx";
+ scl-gpios = <&gpio4 12 0>;
status = "disabled";
};
@@ -525,6 +526,72 @@
#interrupt-cells = <2>;
};
+ uqe: uqe@2400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe", "simple-bus";
+ ranges = <0x0 0x0 0x2400000 0x40000>;
+ reg = <0x0 0x2400000 0x0 0x480>;
+ brg-frequency = <100000000>;
+ bus-frequency = <200000000>;
+
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0 77 0x04 0 77 0x04>;
+ };
+
+ si1: si@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,ls1043-qe-si",
+ "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1043-qe-siram",
+ "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
@@ -579,6 +646,16 @@
status = "disabled";
};
+ ftm0: ftm0@29d0000 {
+ compatible = "fsl,ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x1ee2140 0x0 0x4>;
+ reg-names = "ftm", "FlexTimer1";
+ interrupts = <0 86 0x4>;
+ big-endian;
+ status = "okay";
+ };
+
wdog0: wdog@2ad0000 {
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
@@ -611,7 +688,10 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ configure-gfladj;
};
usb1: usb3@3000000 {
@@ -621,7 +701,10 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ configure-gfladj;
};
usb2: usb3@3100000 {
@@ -631,7 +714,10 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ configure-gfladj;
};
sata: sata@3200000 {
@@ -670,9 +756,9 @@
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 118 0x4>, /* controller interrupt */
- <0 117 0x4>; /* PME interrupt */
- interrupt-names = "intr", "pme";
+ interrupts = <0 117 0x4>, /* PME interrupt */
+ <0 118 0x4>; /* aer interrupt */
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -696,9 +782,9 @@
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 128 0x4>,
- <0 127 0x4>;
- interrupt-names = "intr", "pme";
+ interrupts = <0 127 0x4>,
+ <0 128 0x4>;
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -722,9 +808,9 @@
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 162 0x4>,
- <0 161 0x4>;
- interrupt-names = "intr", "pme";
+ interrupts = <0 161 0x4>,
+ <0 162 0x4>;
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";

375
target/linux/layerscape/patches-5.4/302-dts-0008-arm64-dts-ls1046a-accumulated-change-to-ls1046a-boar.patch Normal file
View File

@ -0,0 +1,375 @@
From 229d32330c7d941b8e04501ad75bc527f6cf1b1c Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Thu, 2 May 2019 16:06:42 -0500
Subject: [PATCH] arm64: dts: ls1046a: accumulated change to ls1046a boards
commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce
Author: Peng Ma <peng.ma@nxp.com>
Date: Wed Jul 25 08:53:07 2018 +0000
dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node
support
add block-offset to support different virtual block offset for qdma
base on soc;
the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual
block,N based on block number of qdma;
Signed-off-by: Peng Ma <peng.ma@nxp.com>
commit 46123df3a174f0d76c8b954a0386e64841453836
Author: Florinel Iordache <florinel.iordache@nxp.com>
Date: Thu Aug 9 12:29:18 2018 +0300
arm64: dts: updates for Unified Backplane driver
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
commit c08136017e8b18eb58b153129487c5dc760afd20
Author: Florinel Iordache <florinel.iordache@nxp.com>
Date: Thu Aug 9 12:23:42 2018 +0300
arm64: dts: ls1046: add support for 10GBase-KR
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
commit 8473f478783f6f601e1c6d7e6afba49a13f3a6a3
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:24:33 2018 +0800
arm64: dts: ls1046a: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 3159fe9263fb145601ccb07fcb9336a68fba4e08
Author: Bao Xiaowei <xiaowei.bao@nxp.com>
Date: Fri Oct 13 11:04:39 2017 +0800
arm64: dts: ls1046a: add the property of IB and OB
Add the property of inbound and outbound windows number for ep
driver.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
commit c8fed58f3c9a0219fda0467791f61abd86eb97f3
Author: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Date: Wed Jan 24 22:56:48 2018 +0530
arm64: dts: freescale: ls1046a: Modify DT nodes for qspi
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
commit 96558859ea3a4af44c0b25441f7574ae6222509a
Author: Ran Wang <ran.wang_1@nxp.com>
Date: Fri Jan 5 15:17:23 2018 +0800
arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node
Enable USB3 HW LPM feature for ls1046a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Tue Jun 13 13:14:26 2017 +0800
arm64: dts: correct the register range of dcfg
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 67c82e3c7b376139d7cee624589bedbc311f8868
Author: jiaheng.fan <jiaheng.fan@nxp.com>
Date: Thu May 11 17:36:33 2017 +0800
arm64: dts: ls1021/ls1043/ls1046: add qdma nodes
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
commit 4a6cef0c83748ee4f6641489fc324bd64095485d
Author: Chenhui Zhao <chenhui.zhao@nxp.com>
Date: Fri May 5 17:53:27 2017 +0800
arm64: dts: ls1046a: add ftm0 node
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 148 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 28 +++-
3 files changed, 174 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -25,6 +25,20 @@
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
+
+ emi1_slot1 = &ls1046mdio_s1;
+ emi1_slot2 = &ls1046mdio_s2;
+ emi1_slot4 = &ls1046mdio_s4;
+
+ sgmii_s1_p1 = &sgmii_phy_s1_p1;
+ sgmii_s1_p2 = &sgmii_phy_s1_p2;
+ sgmii_s1_p3 = &sgmii_phy_s1_p3;
+ sgmii_s1_p4 = &sgmii_phy_s1_p4;
+ sgmii_s4_p1 = &sgmii_phy_s4_p1;
+ qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
+ qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
+ qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
+ qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
};
chosen {
@@ -177,3 +191,137 @@
};
#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy_s2_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&sgmii_phy_s4_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&sgmii_phy_s1_p3>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&sgmii_phy_s1_p4>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* DTSEC9/10GEC1 */
+ phy-handle = <&sgmii_phy_s1_p1>;
+ phy-connection-type = "xgmii";
+ };
+
+ ethernet@f2000 { /* DTSEC10/10GEC2 */
+ phy-handle = <&sgmii_phy_s1_p2>;
+ phy-connection-type = "xgmii";
+ };
+};
+
+&fpga {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ mdio-mux-emi1 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1 */
+
+ /* On-board RGMII1 PHY */
+ ls1046mdio0: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
+ reg = <0x1>;
+ };
+ };
+
+ /* On-board RGMII2 PHY */
+ ls1046mdio1: mdio@1 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
+ reg = <0x2>;
+ };
+ };
+
+ /* Slot 1 */
+ ls1046mdio_s1: mdio@2 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s1_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ sgmii_phy_s1_p2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy_s1_p3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy_s1_p4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ /* Slot 2 */
+ ls1046mdio_s2: mdio@3 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s2_p1: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+ qsgmii_phy_s2_p2: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+ qsgmii_phy_s2_p3: ethernet-phy@a {
+ reg = <0xa>;
+ };
+ qsgmii_phy_s2_p4: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+
+ /* Slot 4 */
+ ls1046mdio_s4: mdio@5 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s4_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ };
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -100,6 +100,7 @@
&qspi {
status = "okay";
+ fsl,qspi-has-second-chip;
qflash0: flash@0 {
compatible = "spansion,m25p80";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -304,7 +304,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
+ reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@@ -376,7 +376,7 @@
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@@ -385,6 +385,7 @@
dmas = <&edma0 1 39>,
<&edma0 1 38>;
dma-names = "tx", "rx";
+ scl-gpios = <&gpio3 12 0>;
status = "disabled";
};
@@ -409,12 +410,13 @@
};
i2c3: i2c@21b0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
+ scl-gpios = <&gpio3 12 0>;
status = "disabled";
};
@@ -544,6 +546,15 @@
status = "disabled";
};
+ ftm0: ftm0@29d0000 {
+ compatible = "fsl,ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x1ee2140 0x0 0x4>;
+ reg-names = "ftm", "FlexTimer1";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
+
wdog0: watchdog@2ad0000 {
compatible = "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
@@ -576,6 +587,8 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
};
usb1: usb@3000000 {
@@ -586,6 +599,8 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
};
usb2: usb@3100000 {
@@ -596,6 +611,8 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
};
sata: sata@3200000 {
@@ -637,6 +654,11 @@
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
};
+ serdes1: serdes@1ea0000 {
+ reg = <0x0 0x1ea0000 0 0x00002000>;
+ compatible = "fsl,serdes-10g";
+ };
+
pcie@3400000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */

540
target/linux/layerscape/patches-5.4/302-dts-0009-arm64-dts-ls1088a-accumulated-change-to-ls1088a-boar.patch Normal file
View File

@ -0,0 +1,540 @@
From 2790ba4aa3e487ac29d6027eb226ed986f0e2769 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Thu, 2 May 2019 16:10:03 -0500
Subject: [PATCH] arm64: dts: ls1088a: accumulated change to ls1088a boards
commit f967940f2fb73bc7ec676dbad9f32fbf4e7fea2b
Author: Pengbo Mu <pengbo.mu@nxp.com>
Date: Fri Jul 13 16:19:36 2018 +0800
arm64: dts: ls1088a: add snps incr burst type adjustment in usb0 &
usb1
This property could fix the defect that external usb device always
prints this error log --- 'reset SuperSpeed USB device number n
using
xhci_hcd' when system power on.
Signed-off-by: Pengbo Mu <pengbo.mu@nxp.com>
commit 46123df3a174f0d76c8b954a0386e64841453836
Author: Florinel Iordache <florinel.iordache@nxp.com>
Date: Thu Aug 9 12:29:18 2018 +0300
arm64: dts: updates for Unified Backplane driver
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
commit 3b214bd42d47ebe7b6af925a3ffcf09aaaaabfb9
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Sat Apr 28 00:20:48 2018 +0530
arm64: dts: ls1088: add dma-cohernet property in fsl-mc node
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit 240b04a98171f6774d1c3c498f8cb21f4411ac5f
Author: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Thu Apr 26 12:26:54 2018 +0300
arm64: dts: ls1088a: move fsl-mc node as a child of soc
Move the fsl-mc hardware manager node in the soc node because all
the
soc settings (such as 'dma-ranges') also apply to the fsl-mc and
need
to be propagated to it.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
commit 3f2f50950f763d1335181ce374a11ed118abf0fa
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Wed Apr 25 09:43:47 2018 +0530
arm64: dts: ls1088: add dma ranges property
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit 6afd0157e8fa2510790537855c86f8a7c1431abe
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:25:38 2018 +0800
arm64: dts: ls1088a: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 0f8432c30c44771f9180aa7bf7580ad1d7e7c9d3
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Mon Feb 26 10:40:37 2018 +0530
arm64: dts: ls1088a: add dma coherent property in smmu node
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit 6417c66b823ab380cf73ee252a998d98b28f0180
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Fri Feb 2 00:04:41 2018 +0530
arm64: dts: freescale: ls1088a: Modify DT nodes for qspi
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
commit 01a1ea9e781d307ab87da95043ec898736495fff
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Thu Nov 2 10:36:48 2017 +0800
arm64: dts: ls1088a: correct the i2c clock to 1/8 platform pll
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 60122f1192e1cc23e5952468cc5a884287d64907
Author: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Date: Thu Sep 7 10:08:31 2017 +0530
arm64: dts: ls1088a: Add iommu-map property for pci
This patch adds iommu-map property for PCIe, which enables
SMMU for these devices on LS1088.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
commit 43c4d0cf074106b411280c5b2be75d5d6e63fb01
Author: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
Date: Mon Aug 21 11:43:07 2017 +0300
arm64: dts: ls1088a: add backplane support
Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
commit 57d49424694f72adbf7cf1dbeff38704f0d65359
Author: Ashish Kumar <Ashish.Kumar@nxp.com>
Date: Mon Jun 19 18:32:13 2017 +0530
arm64: dts: ls1088: Add Reboot node in dtsi
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
commit ee950989a7babc240153a20fe468573e13d61f98
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Thu May 11 14:59:28 2017 +0800
arm64: dts: ls1088a: add ftm0 nodes
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 6d3a96446a7ffccb0b9936b616d855c8d5572bce
Author: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Date: Wed May 3 14:26:35 2017 +0000
arm64: dts: fsl/ls1088,ls208x: Add mdio and phy nodes
Add mdio and phy nodes for the following FSL platforms:
- LS1088A RDB
- LS2080A QDS & RDB
- LS2088A QDS, RDB & simu
Contains contributions from patches by the following authors:
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava
<pratiyush.srivastava@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
commit 971ff2e74cfebb84286ec3e191f5910dded4bd41
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Thu May 4 18:04:44 2017 +0530
arm64: dts: ls1088a: Add QSPI node for QDS, RDB
This is temporary patch, will rewrite for open source
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
commit c61036e6dfe264d61cc213293040d873d863e8ac
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Thu Apr 27 23:35:15 2017 +0530
arm64: dts: add iommu-map property in fsl-mc node
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit a4412cc510162a900d10c8ca4add71defb3f2d97
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Wed Apr 19 22:26:15 2017 +0530
arm64: dts: add smmu device node in LS1088 devicetree
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 50 ++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 104 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 108 +++++++++++++++++++++-
3 files changed, 261 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
@@ -131,6 +131,30 @@
};
};
+&qspi {
+ status = "okay";
+ fsl,qspi-has-second-chip;
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+
+ qflash1: s25fs512s@1 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
&duart0 {
status = "okay";
};
@@ -146,3 +170,29 @@
&sata {
status = "okay";
};
+
+&pcs_mdio1 {
+ pcs_phy1: ethernet-phy@0 {
+ backplane-mode = "10gbase-kr";
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0x840 0x40>;/* lane B */
+ };
+};
+
+&pcs_mdio2 {
+ pcs_phy2: ethernet-phy@0 {
+ backplane-mode = "10gbase-kr";
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0x800 0x40>;/* lane A */
+ };
+};
+
+/* Update DPMAC connections to backplane PHYs, under SerDes 0x1D_0xXX.
+ * &dpmac1 {
+ * phy-handle = <&pcs_phy1>;
+ * };
+ */
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -74,6 +74,31 @@
};
};
+&qspi {
+ status = "okay";
+ fsl,qspi-has-second-chip;
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+
+ qflash1: s25fs512s@1 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+
+};
+
&duart0 {
status = "okay";
};
@@ -97,3 +122,82 @@
&usb1 {
status = "okay";
};
+
+&emdio1 {
+ /* Freescale F104 PHY1 */
+ mdio1_phy1: emdio1_phy@1 {
+ reg = <0x1c>;
+ phy-connection-type = "qsgmii";
+ };
+ mdio1_phy2: emdio1_phy@2 {
+ reg = <0x1d>;
+ phy-connection-type = "qsgmii";
+ };
+ mdio1_phy3: emdio1_phy@3 {
+ reg = <0x1e>;
+ phy-connection-type = "qsgmii";
+ };
+ mdio1_phy4: emdio1_phy@4 {
+ reg = <0x1f>;
+ phy-connection-type = "qsgmii";
+ };
+ /* F104 PHY2 */
+ mdio1_phy5: emdio1_phy@5 {
+ reg = <0x0c>;
+ phy-connection-type = "qsgmii";
+ };
+ mdio1_phy6: emdio1_phy@6 {
+ reg = <0x0d>;
+ phy-connection-type = "qsgmii";
+ };
+ mdio1_phy7: emdio1_phy@7 {
+ reg = <0x0e>;
+ phy-connection-type = "qsgmii";
+ };
+ mdio1_phy8: emdio1_phy@8 {
+ reg = <0x0f>;
+ phy-connection-type = "qsgmii";
+ };
+};
+
+&emdio2 {
+ /* Aquantia AQR105 10G PHY */
+ mdio2_phy1: emdio2_phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 2 0x4>;
+ reg = <0x0>;
+ phy-connection-type = "xfi";
+ };
+};
+
+/* DPMAC connections to external PHYs
+ * based on LS1088A RM RevC - $24.1.2 SerDes Options
+ */
+/* DPMAC1 is 10G SFP+, fixed link */
+&dpmac2 {
+ phy-handle = <&mdio2_phy1>;
+};
+&dpmac3 {
+ phy-handle = <&mdio1_phy5>;
+};
+&dpmac4 {
+ phy-handle = <&mdio1_phy6>;
+};
+&dpmac5 {
+ phy-handle = <&mdio1_phy7>;
+};
+&dpmac6 {
+ phy-handle = <&mdio1_phy8>;
+};
+&dpmac7 {
+ phy-handle = <&mdio1_phy1>;
+};
+&dpmac8 {
+ phy-handle = <&mdio1_phy2>;
+};
+&dpmac9 {
+ phy-handle = <&mdio1_phy3>;
+};
+&dpmac10 {
+ phy-handle = <&mdio1_phy4>;
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -185,6 +185,19 @@
clock-output-names = "sysclk";
};
+ rstcr: syscon@1e60000 {
+ compatible = "fsl,ls1088a-rstcr", "syscon";
+ reg = <0x0 0x1e60000 0x0 0x4>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&rstcr>;
+ offset = <0x0>;
+ mask = <0x02>;
+ };
+
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -205,6 +218,11 @@
little-endian;
};
+ serdes1: serdes@1ea0000 {
+ reg = <0x0 0x1ea0000 0 0x00002000>;
+ compatible = "fsl,serdes-10g";
+ };
+
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
@@ -325,6 +343,72 @@
#interrupt-cells = <2>;
};
+ /* TODO: WRIOP (CCSR?) */
+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
+ * E-MDIO1: 0x1_6000
+ */
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8B96000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian; /* force the driver in LE mode */
+
+ /* Not necessary on the QDS, but needed on the RDB */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
+ * E-MDIO2: 0x1_7000
+ */
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8B97000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian; /* force the driver in LE mode */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio1: mdio@0x8c07000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c07000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio2: mdio@0x8c0b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0b000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio3: mdio@0x8c0f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0f000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio4: mdio@0x8c13000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c13000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x2240000 0x0 0x20000>;
@@ -335,13 +419,20 @@
status = "disabled";
};
+ ftm0: ftm0@2800000 {
+ compatible = "fsl,ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ interrupts = <0 44 4>;
+ };
+
i2c0: i2c@2000000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 7>;
+ scl-gpios = <&gpio3 30 0>;
status = "disabled";
};
@@ -405,6 +496,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
@@ -418,6 +510,17 @@
dma-coherent;
status = "disabled";
};
+ qspi: spi@20c0000 {
+ compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "qspi_en", "qspi";
+ };
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
@@ -474,6 +577,7 @@
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
@@ -499,6 +603,7 @@
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
@@ -524,6 +629,7 @@
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,

959
target/linux/layerscape/patches-5.4/302-dts-0010-arm64-dts-ls208xa-accumulated-change-to-ls208xa-boar.patch Normal file
View File

@ -0,0 +1,959 @@
From 9d8de47b617baa4fa92d9a1502904c0373f80384 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Thu, 2 May 2019 16:12:40 -0500
Subject: [PATCH] arm64: dts: ls208xa: accumulated change to ls208xa boards
commit 46123df3a174f0d76c8b954a0386e64841453836
Author: Florinel Iordache <florinel.iordache@nxp.com>
Date: Thu Aug 9 12:29:18 2018 +0300
arm64: dts: updates for Unified Backplane driver
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
commit 76a741dbb9b93ea9ab2f6122b8df5bc4f0db7676
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Sat Apr 28 00:20:16 2018 +0530
arm64: dts: ls208x: add dma-cohernet property in fsl-mc node
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit f6309e9dc8e0c6171a43fd6759123b5de1c574aa
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon Apr 2 16:27:23 2018 +0800
arm64: dts: ls208xa: add dts entry for A-010650
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 8c37bad2038a210a4f0a369fd946aaae4317eac4
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Fri Apr 20 17:14:10 2018 +0530
arm64: dts: ls208x: add dma ranges property
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
Author: Changming Huang <jerry.huang@nxp.com>
Date: Wed Apr 19 12:49:50 2017 +0800
arm/arm64: dts: Add property snps incr burst type adjustment for
INCR burst type for dwc3
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
commit dbb65ea8ee1d46067e756c6d64c7fe66a0058f49
Author: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Mon Mar 5 12:37:04 2018 +0530
arm64: dts: ls208x: remove NXP Erratum A008585 from LS2088A.
NXP Erratum A008585 affects A57 core cluster used in LS2085rev1.
However this problem has been fixed in A72 core cluster used in
LS2088.
Therefore remove the erratum from LS2088A. Keeping it only in
LS2085.
Cc: <stable@vger.kernel.org> # 4.14
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Sandeep Malik <sandeep.malik@nxp.com>
Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
commit 85f41b0f6abe6b9d7d303790bb3712ed559890e9
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Mon Feb 26 10:39:54 2018 +0530
arm64: dts: ls208xa: add dma coherent property in smmu node
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
commit e910d8b78b823a625451b1da7ae7499dadde2ae9
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Thu Feb 1 23:49:56 2018 +0530
arm64: dts: freescale: ls208xa: Modify DT nodes for qspi
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
commit 7654ef78c8c85de3a43dfa0dffd572d589ea1332
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Wed Nov 1 10:34:04 2017 +0800
arm64: dts: ls208xa: correct the i2c clock to 1/2 platform pll
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit efdb129228baa6a999c06072338b979d783d7b60
Author: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Date: Thu Aug 31 14:45:02 2017 +0530
arm64: dts: ls208xa: Add iommu-map property for pci
This patch adds iommu-map property for PCIe, which enables
SMMU for these devices on LS208xA devices.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
commit 45af5d025eafaf4a85000e16e5f47992de663ff6
Author: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
Date: Mon Aug 21 11:46:59 2017 +0300
arm64: dts: ls2088a: update backplane support with dpmac connections
Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
commit b2ede6c088a883fceb348e8659253b2c7cdeeff8
Author: Santan Kumar <santan.kumar@nxp.com>
Date: Thu Jun 22 13:04:00 2017 +0530
arm64: dts: ls2088ardb: Update nodes for QSPI
-As per board design, different QSPI flash is connected on
boards, hence change QSPI flash node from s25fl256s1 to s25fs512ss
in
device tree.
-Enable fast-read support in QSPI node.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
commit d5324a75c56e9f9210113e51cffa846a86b50fbd
Author: Santan Kumar <santan.kumar@nxp.com>
Date: Mon Jun 19 15:26:03 2017 +0530
arm64: dts: ls2081ardb: Update nodes for QSPI, SATA, INA220
Update ls2081ardb.dts for below nodes:
-As per updated board design, different QSPI flash is connected on
boards, hence change QSPI flash node from n25q512a to s25fs512ss
in
device tree.
-Enable dual flash support in QSPI node.
-Add DTS node for INA220.
-Enable SATA node.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Tao Yang <b31903@freescale.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
commit 43d506fa19e1e50e4c2e4f9689ad3c60d9a06d71
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Thu May 11 08:42:19 2017 +0800
arm64: dts: ls208x: add property for PCA954x Mux device
PCA954x Mux device should never be turned-off after power-on. if
device tree contians "i2c-mux-never-disable" property for pca954x
device node, it can ensure that skip disabling PCA954x Mux device.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 6d3a96446a7ffccb0b9936b616d855c8d5572bce
Author: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Date: Wed May 3 14:26:35 2017 +0000
arm64: dts: fsl/ls1088,ls208x: Add mdio and phy nodes
Add mdio and phy nodes for the following FSL platforms:
- LS1088A RDB
- LS2080A QDS & RDB
- LS2088A QDS, RDB & simu
Contains contributions from patches by the following authors:
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava
<pratiyush.srivastava@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
commit 0443625ea24bc4ea315c30b718712254c588bd18
Author: Suresh Gupta <suresh.gupta@nxp.com>
Date: Fri May 5 13:54:22 2017 +0530
arm64: dts: ls208xa: Add QSPI Flash node for RDB
This is temporary patch, will rewrite for open source
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
commit ed0ce1d49aa72d12ea54f82d3771a377c68af37e
Author: Priyanka Jain <priyanka.jain@nxp.com>
Date: Thu Apr 13 16:49:40 2017 +0530
arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDB
This patch add support for NXP LS2081ARDB board which has
LS2081A SoC.
LS2081A SoC is 40-pin derivative of LS2088A SoC
So, from functional perspective both are same.
Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
commit e4fb842554a5e7b8c3f6e3c243222dbe4515aee3
Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Thu Apr 27 15:01:54 2017 +0800
arm64: dts: ls208xa: add ftm0 nodes
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
commit 64c3e2c3a7ddc89c3c23c012ee364f2c014524d2
Author: costi <constantin.tudor@freescale.com>
Date: Fri Mar 3 18:08:28 2017 +0200
arm64: dts: fsl-ls2088: Add mdio/phy devices
Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
Author: Po Liu <po.liu@nxp.com>
Date: Fri Sep 30 17:11:36 2016 +0800
arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
Some platforms(NXP Layerscape for example) aer/pme interrupts was
not
MSI/MSI-X/INTx but using interrupt line independently. This patch
add "aer", "pme" interrupt-names for aer/pme interrupt.
With the interrupt-names "aer", "pme" code could probe aer/pme
interrupt
line for pcie root port, replace the aer/pme interrupt service irqs.
This is intend to fixup the Layerscape platforms which aer/pmes
interrupts
was not MSI/MSI-X/INTx, but using interrupt line independently.
Since the interrupt-names "intr" never been used. Remove it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
commit 64d859836d3d194e8bc926bb951fd21859689824
Author: Nipun Gupta <nipun.gupta@nxp.com>
Date: Mon Dec 5 05:20:51 2016 +0530
arm64: dts: ls208xa: Comply with the new iommu binding for fsl_mc
fsl-mc bus support the new iommu-map property. Comply to this
binding
for fsl_mc bus.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 62 +++++++++
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 80 +++++++++++
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 12 ++
arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 120 ++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 80 +++++++++++
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 11 +-
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 155 +++++++++++++++++++--
8 files changed, 505 insertions(+), 16 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -23,3 +23,65 @@
stdout-path = "serial0:115200n8";
};
};
+
+&ifc {
+ boardctrl: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
+ reg = <3 0 0x300>; /* TODO check address */
+ ranges = <0 3 0 0x300>;
+
+ mdio_mux_emi1 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&emdio1>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1_MDIO */
+
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ /* Child MDIO buses, one for each riser card:
+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
+ * VSC8234 PHYs on the riser cards.
+ */
+
+ mdio_mux3: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio0_phy12: mdio_phy0@1c {
+ reg = <0x1c>;
+ phy-connection-type = "sgmii";
+ };
+ mdio0_phy13: mdio_phy1@1d {
+ reg = <0x1d>;
+ phy-connection-type = "sgmii";
+ };
+ mdio0_phy14: mdio_phy2@1e {
+ reg = <0x1e>;
+ phy-connection-type = "sgmii";
+ };
+ mdio0_phy15: mdio_phy3@1f {
+ reg = <0x1f>;
+ phy-connection-type = "sgmii";
+ };
+ };
+ };
+ };
+};
+
+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
+&dpmac9 {
+ phy-handle = <&mdio0_phy12>;
+};
+&dpmac10 {
+ phy-handle = <&mdio0_phy13>;
+};
+&dpmac11 {
+ phy-handle = <&mdio0_phy14>;
+};
+&dpmac12 {
+ phy-handle = <&mdio0_phy15>;
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -23,3 +23,83 @@
stdout-path = "serial1:115200n8";
};
};
+
+&emdio1 {
+ status = "disabled";
+ /* CS4340 PHYs */
+ mdio1_phy1: emdio1_phy@1 {
+ reg = <0x10>;
+ phy-connection-type = "xfi";
+ };
+ mdio1_phy2: emdio1_phy@2 {
+ reg = <0x11>;
+ phy-connection-type = "xfi";
+ };
+ mdio1_phy3: emdio1_phy@3 {
+ reg = <0x12>;
+ phy-connection-type = "xfi";
+ };
+ mdio1_phy4: emdio1_phy@4 {
+ reg = <0x13>;
+ phy-connection-type = "xfi";
+ };
+};
+
+&emdio2 {
+ /* AQR405 PHYs */
+ mdio2_phy1: emdio2_phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 1 0x4>; /* Level high type */
+ reg = <0x0>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy2: emdio2_phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 2 0x4>; /* Level high type */
+ reg = <0x1>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy3: emdio2_phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 4 0x4>; /* Level high type */
+ reg = <0x2>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy4: emdio2_phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 5 0x4>; /* Level high type */
+ reg = <0x3>;
+ phy-connection-type = "xfi";
+ };
+};
+
+/* Update DPMAC connections to external PHYs, under the assumption of
+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
+ */
+/* Leave Cortina nodes commented out until driver is integrated
+ *&dpmac1 {
+ * phy-handle = <&mdio1_phy1>;
+ *};
+ *&dpmac2 {
+ * phy-handle = <&mdio1_phy2>;
+ *};
+ *&dpmac3 {
+ * phy-handle = <&mdio1_phy3>;
+ *};
+ *&dpmac4 {
+ * phy-handle = <&mdio1_phy4>;
+ *};
+ */
+
+&dpmac5 {
+ phy-handle = <&mdio2_phy1>;
+};
+&dpmac6 {
+ phy-handle = <&mdio2_phy2>;
+};
+&dpmac7 {
+ phy-handle = <&mdio2_phy3>;
+};
+&dpmac8 {
+ phy-handle = <&mdio2_phy4>;
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -118,6 +118,18 @@
};
};
+&timer {
+ fsl,erratum-a008585;
+};
+
+&usb0 {
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+};
+
+&usb1 {
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+};
+
&pcie1 {
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x10 0x00000000 0x0 0x00002000>; /* configuration space */
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
@@ -22,3 +22,123 @@
stdout-path = "serial0:115200n8";
};
};
+
+&ifc {
+ boardctrl: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
+ reg = <3 0 0x300>; /* TODO check address */
+ ranges = <0 3 0 0x300>;
+
+ mdio_mux_emi1 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&emdio1>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1_MDIO */
+
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ /* Child MDIO buses, one for each riser card:
+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
+ * VSC8234 PHYs on the riser cards.
+ */
+
+ mdio_mux3: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio0_phy12: mdio_phy0@1c {
+ reg = <0x1c>;
+ phy-connection-type = "sgmii";
+ };
+ mdio0_phy13: mdio_phy1@1d {
+ reg = <0x1d>;
+ phy-connection-type = "sgmii";
+ };
+ mdio0_phy14: mdio_phy2@1e {
+ reg = <0x1e>;
+ phy-connection-type = "sgmii";
+ };
+ mdio0_phy15: mdio_phy3@1f {
+ reg = <0x1f>;
+ phy-connection-type = "sgmii";
+ };
+ };
+ };
+ };
+};
+
+&pcs_mdio1 {
+ pcs_phy1: ethernet-phy@0 {
+ backplane-mode = "10gbase-kr";
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0x9C0 0x40>;/* lane H */
+ };
+};
+
+&pcs_mdio2 {
+ pcs_phy2: ethernet-phy@0 {
+ backplane-mode = "10gbase-kr";
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0x980 0x40>;/* lane G */
+ };
+};
+
+&pcs_mdio3 {
+ pcs_phy3: ethernet-phy@0 {
+ backplane-mode = "10gbase-kr";
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0x940 0x40>;/* lane F */
+ };
+};
+
+&pcs_mdio4 {
+ pcs_phy4: ethernet-phy@0 {
+ backplane-mode = "10gbase-kr";
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0x900 0x40>;/* lane E */
+ };
+};
+
+/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
+ * &dpmac1 {
+ * phy-handle = <&pcs_phy1>;
+ * };
+ *
+ * &dpmac2 {
+ * phy-handle = <&pcs_phy2>;
+ * };
+ *
+ * &dpmac3 {
+ * phy-handle = <&pcs_phy3>;
+ * };
+ *
+ * &dpmac4 {
+ * phy-handle = <&pcs_phy4>;
+ * };
+ */
+
+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
+&dpmac9 {
+ phy-handle = <&mdio0_phy12>;
+};
+&dpmac10 {
+ phy-handle = <&mdio0_phy13>;
+};
+&dpmac11 {
+ phy-handle = <&mdio0_phy14>;
+};
+&dpmac12 {
+ phy-handle = <&mdio0_phy15>;
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
@@ -22,3 +22,83 @@
stdout-path = "serial1:115200n8";
};
};
+
+&emdio1 {
+ status = "disabled";
+ /* CS4340 PHYs */
+ mdio1_phy1: emdio1_phy@1 {
+ reg = <0x10>;
+ phy-connection-type = "xfi";
+ };
+ mdio1_phy2: emdio1_phy@2 {
+ reg = <0x11>;
+ phy-connection-type = "xfi";
+ };
+ mdio1_phy3: emdio1_phy@3 {
+ reg = <0x12>;
+ phy-connection-type = "xfi";
+ };
+ mdio1_phy4: emdio1_phy@4 {
+ reg = <0x13>;
+ phy-connection-type = "xfi";
+ };
+};
+
+&emdio2 {
+ /* AQR405 PHYs */
+ mdio2_phy1: emdio2_phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 1 0x4>; /* Level high type */
+ reg = <0x0>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy2: emdio2_phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 2 0x4>; /* Level high type */
+ reg = <0x1>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy3: emdio2_phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 4 0x4>; /* Level high type */
+ reg = <0x2>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy4: emdio2_phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 5 0x4>; /* Level high type */
+ reg = <0x3>;
+ phy-connection-type = "xfi";
+ };
+};
+
+/* Update DPMAC connections to external PHYs, under the assumption of
+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
+ */
+/* Leave Cortina PHYs commented out until proper driver is integrated
+ *&dpmac1 {
+ * phy-handle = <&mdio1_phy1>;
+ *};
+ *&dpmac2 {
+ * phy-handle = <&mdio1_phy2>;
+ *};
+ *&dpmac3 {
+ * phy-handle = <&mdio1_phy3>;
+ *};
+ *&dpmac4 {
+ * phy-handle = <&mdio1_phy4>;
+ *};
+ */
+
+&dpmac5 {
+ phy-handle = <&mdio2_phy1>;
+};
+&dpmac6 {
+ phy-handle = <&mdio2_phy2>;
+};
+&dpmac7 {
+ phy-handle = <&mdio2_phy3>;
+};
+&dpmac8 {
+ phy-handle = <&mdio2_phy4>;
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
@@ -129,6 +129,7 @@
&qspi {
status = "okay";
+ fsl,qspi-has-second-chip;
flash0: s25fl256s1@0 {
#address-cells = <1>;
#size-cells = <1>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -49,6 +49,7 @@
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-mux-never-disable;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
@@ -108,7 +109,15 @@
};
&qspi {
- status = "disabled";
+ status = "okay";
+ flash0: s25fs512s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
};
&sata0 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -114,13 +114,12 @@
};
};
- timer {
+ timer: timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
<1 14 4>, /* Physical Non-Secure PPI, active-low */
<1 11 4>, /* Virtual PPI, active-low */
<1 10 4>; /* Hypervisor PPI, active-low */
- fsl,erratum-a008585;
};
pmu {
@@ -560,15 +559,126 @@
#interrupt-cells = <2>;
};
+ /* TODO: WRIOP (CCSR?) */
+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
+ * E-MDIO1: 0x1_6000
+ */
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8B96000 0x0 0x1000>;
+ device_type = "mdio"; /* TODO: is this necessary? */
+ little-endian; /* force the driver in LE mode */
+
+ /* Not necessary on the QDS, but needed on the RDB */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
+ * E-MDIO2: 0x1_7000
+ */
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8B97000 0x0 0x1000>;
+ device_type = "mdio"; /* TODO: is this necessary? */
+ little-endian; /* force the driver in LE mode */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio1: mdio@0x8c07000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c07000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio2: mdio@0x8c0b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0b000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio3: mdio@0x8c0f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0f000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio4: mdio@0x8c13000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c13000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio5: mdio@0x8c17000 {
+ status = "disabled";
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c17000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio6: mdio@0x8c1b000 {
+ status = "disabled";
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1b000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio7: mdio@0x8c1f000 {
+ status = "disabled";
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1f000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio8: mdio@0x8c23000 {
+ status = "disabled";
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c23000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
i2c0: i2c@2000000 {
status = "disabled";
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
clock-names = "i2c";
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen 4 1>;
+ scl-gpios = <&gpio3 10 0>;
};
i2c1: i2c@2010000 {
@@ -579,7 +689,7 @@
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
clock-names = "i2c";
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen 4 1>;
};
i2c2: i2c@2020000 {
@@ -590,7 +700,7 @@
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
clock-names = "i2c";
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen 4 1>;
};
i2c3: i2c@2030000 {
@@ -601,7 +711,7 @@
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
clock-names = "i2c";
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen 4 1>;
};
ifc: ifc@2240000 {
@@ -633,8 +743,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
- interrupts = <0 108 0x4>; /* Level high type */
- interrupt-names = "intr";
+ interrupts = <0 108 0x4>; /* aer interrupt */
+ interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -642,6 +752,7 @@
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
@@ -654,8 +765,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
- interrupts = <0 113 0x4>; /* Level high type */
- interrupt-names = "intr";
+ interrupts = <0 113 0x4>; /* aer interrupt */
+ interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -663,6 +774,7 @@
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
@@ -675,8 +787,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
- interrupts = <0 118 0x4>; /* Level high type */
- interrupt-names = "intr";
+ interrupts = <0 118 0x4>; /* aer interrupt */
+ interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -684,6 +796,7 @@
num-viewport = <256>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
@@ -696,8 +809,8 @@
pcie4: pcie@3700000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
- interrupts = <0 123 0x4>; /* Level high type */
- interrupt-names = "intr";
+ interrupts = <0 123 0x4>; /* aer interrupt */
+ interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -705,6 +818,7 @@
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
@@ -754,11 +868,22 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
+ serdes1: serdes@1ea0000 {
+ reg = <0x0 0x1ea0000 0 0x00002000>;
+ compatible = "fsl,serdes-10g";
+ };
+
ccn@4000000 {
compatible = "arm,ccn-504";
reg = <0x0 0x04000000 0x0 0x01000000>;
interrupts = <0 12 4>;
};
+
+ ftm0: ftm0@2800000 {
+ compatible = "fsl,ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ interrupts = <0 44 4>;
+ };
};
ddr1: memory-controller@1080000 {

156
target/linux/layerscape/patches-5.4/302-dts-0011-ARM-dts-accumulated-change.patch Normal file
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@ -0,0 +1,156 @@
From a9f1c1d3e410596d0a39fd92562cc48ef960b1b7 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Fri, 5 Oct 2018 18:33:49 -0500
Subject: [PATCH] ARM: dts: accumulated change
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm/boot/dts/ls1021a-qds.dts | 15 +++++++++++++++
arch/arm/boot/dts/ls1021a-twr.dts | 15 +++++++++++++++
arch/arm/boot/dts/ls1021a.dtsi | 29 ++++++++++++++++++++++++-----
3 files changed, 54 insertions(+), 5 deletions(-)
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -126,6 +126,21 @@
};
};
+&qspi {
+ num-cs = <2>;
+ status = "okay";
+
+ qflash0: s25fl128s@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy1c>;
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -144,6 +144,21 @@
};
};
+&qspi {
+ num-cs = <2>;
+ status = "okay";
+
+ qflash0: n25q128a13@0 {
+ compatible = "n25q128a13", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy2>;
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -167,12 +167,13 @@
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
+ big-endian;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1021a-dcfg", "syscon";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
+ reg = <0x0 0x1ee0000 0x0 0x1000>;
big-endian;
};
@@ -371,7 +372,7 @@
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@@ -380,11 +381,12 @@
clocks = <&clockgen 4 1>;
dma-names = "tx", "rx";
dmas = <&edma0 1 39>, <&edma0 1 38>;
+ fsl-scl-gpio = <&gpio3 23 0>;
status = "disabled";
};
i2c1: i2c@2190000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
@@ -393,6 +395,7 @@
clocks = <&clockgen 4 1>;
dma-names = "tx", "rx";
dmas = <&edma0 1 37>, <&edma0 1 36>;
+ fsl-scl-gpio = <&gpio3 23 0>;
status = "disabled";
};
@@ -579,6 +582,16 @@
status = "disabled";
};
+ ftm0: ftm0@29d0000 {
+ compatible = "fsl,ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x1ee2140 0x0 0x4>;
+ reg-names = "ftm", "FlexTimer1";
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ status = "okay";
+ };
+
pwm1: pwm@29e0000 {
compatible = "fsl,vf610-ftm-pwm";
#pwm-cells = <3>;
@@ -861,6 +874,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
@@ -869,7 +884,9 @@
reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupt-names = "pme", "aer";
fsl,pcie-scfg = <&scfg 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -893,7 +910,9 @@
reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupt-names = "pme", "aer";
fsl,pcie-scfg = <&scfg 1>;
#address-cells = <3>;
#size-cells = <2>;

63
target/linux/layerscape/patches-5.4/302-dts-0012-arm64-dts-ls1046a-add-smmu-node.patch Normal file
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@ -0,0 +1,63 @@
From 233d5936fb01dc7b47641e10354f7cc34124c592 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Tue, 6 Feb 2018 14:27:41 +0200
Subject: [PATCH] arm64: dts: ls1046a: add smmu node
This allows for the SMMU device to be probed by the SMMU kernel driver.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 42 ++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -229,6 +229,48 @@
bus-width = <4>;
};
+ smmu: iommu@9000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x9000000 0 0x400000>;
+ dma-coherent;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
scfg: scfg@1570000 {
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;

63
target/linux/layerscape/patches-5.4/302-dts-0013-arm64-dts-ls1043a-add-smmu-node.patch Normal file
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@ -0,0 +1,63 @@
From 6b81f85d194bf15cf91ed3b4a8aec2d1ed2849a8 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Tue, 3 Apr 2018 17:15:44 +0300
Subject: [PATCH] arm64: dts: ls1043a: add smmu node
This allows for the SMMU device to be probed by the SMMU kernel driver.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 42 ++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -226,6 +226,48 @@
clocks = <&sysclk>;
};
+ smmu: iommu@9000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x9000000 0 0x400000>;
+ dma-coherent;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
scfg: scfg@1570000 {
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;

38
target/linux/layerscape/patches-5.4/302-dts-0014-arm64-dts-ls104xa-set-mask-to-drop-TBU-ID-from-Strea.patch Normal file
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@ -0,0 +1,38 @@
From 66307f9e693bd4822a683fac8cf1f63533822c18 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Thu, 3 May 2018 18:05:43 +0300
Subject: [PATCH] arm64: dts: ls104xa: set mask to drop TBU ID from StreamID
The StreamID entering the SMMU is actually a concatenation of the
SMMU TBU ID and the ICID configured in software.
Since the TBU ID is internal to the SoC and since we want that the
actual the ICID configured in software to enter the SMMU witout any
additional set bits, mask out the TBU ID bits and leave only the
relevant ICID bits to enter SMMU.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
2 files changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -230,6 +230,7 @@
compatible = "arm,mmu-500";
reg = <0 0x9000000 0 0x400000>;
dma-coherent;
+ stream-match-mask = <0x7f00>;
#global-interrupts = <2>;
#iommu-cells = <1>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -233,6 +233,7 @@
compatible = "arm,mmu-500";
reg = <0 0x9000000 0 0x400000>;
dma-coherent;
+ stream-match-mask = <0x7f00>;
#global-interrupts = <2>;
#iommu-cells = <1>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

35
target/linux/layerscape/patches-5.4/302-dts-0015-arm64-dts-ls104x-add-missing-dma-ranges-property.patch Normal file
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@ -0,0 +1,35 @@
From f656c67b9522f18e38394fe5b6e00302c0c8ceb8 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Thu, 17 May 2018 11:40:07 +0300
Subject: [PATCH] arm64: dts: ls104x: add missing dma ranges property
These chips have a 48-bit address size so make sure that the dma-ranges
reflects this. Otherwise the linux kernel's dma sub-system will set
the default dma masks to full 64-bit, badly breaking dmas.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
2 files changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -218,6 +218,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -190,6 +190,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";

67
target/linux/layerscape/patches-5.4/302-dts-0016-arm64-dts-ls104x-add-iommu-map-to-pci-controllers.patch Normal file
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@ -0,0 +1,67 @@
From 317d4e577ede33f226d24bd12a8edbaafee22e57 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Thu, 17 May 2018 11:56:27 +0300
Subject: [PATCH] arm64: dts: ls104x: add iommu-map to pci controllers
The pci controllers are also behind the smmu so add the iommu-map
property to reflect this. The bootloader needs to patch the stream id
ranges to some sane values.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
2 files changed, 6 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -807,6 +807,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -833,6 +834,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -859,6 +861,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -715,6 +715,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -751,6 +752,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -787,6 +789,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
+ iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */

67
target/linux/layerscape/patches-5.4/302-dts-0017-arm64-dts-ls104x-make-dma-coherent-global-to-the-SoC.patch Normal file
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@ -0,0 +1,67 @@
From b1e679aba75e5e137c70bc76169c34835ef0e474 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Tue, 24 Jul 2018 13:11:03 +0300
Subject: [PATCH] arm64: dts: ls104x: make dma-coherent global to the SoC
These SoCs are really completely dma coherent in their entirety so add
the dma-coherent property at the soc level in the device tree and drop
the instances where it's specifically added to a few select devices.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 +----
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
2 files changed, 2 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -219,6 +219,7 @@
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ dma-coherent;
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
@@ -771,7 +772,6 @@
reg-names = "ahci", "sata-ecc";
interrupts = <0 69 0x4>;
clocks = <&clockgen 4 0>;
- dma-coherent;
};
msi1: msi-controller1@1571000 {
@@ -806,7 +806,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
@@ -833,7 +832,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
@@ -860,7 +858,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -191,6 +191,7 @@
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ dma-coherent;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";

193
target/linux/layerscape/patches-5.4/302-dts-0018-arm64-dts-ls104x-use-a-pseudo-bus-to-constrain-usb-d.patch Normal file
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@ -0,0 +1,193 @@
From a6a86473350c7dcbae61afa1e926941d76ca17ed Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Thu, 20 Sep 2018 13:46:54 +0300
Subject: [PATCH] arm64: dts: ls104x: use a pseudo-bus to constrain usb dma
size
Wrap the usb controllers in an intermediate simple-bus and use it to
constrain the dma address size of these usb controllers to the 40 bits
that they generate toward the interconnect.
This is required because the SoC uses 48 bits address sizes and this
mismatch would lead to smmu context faults because the usb generates
40-bit addresses while the smmu page tables are populated with 48-bit
wide addresses.
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 82 ++++++++++++++------------
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 76 +++++++++++++-----------
2 files changed, 87 insertions(+), 71 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -726,43 +726,51 @@
<&clockgen 4 0>;
};
- usb0: usb3@2f00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <0 60 0x4>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- usb3-lpm-capable;
- snps,dis-u1u2-when-u3-quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- configure-gfladj;
- };
+ usb_aux_bus: usb_aux_bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
- usb1: usb3@3000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3000000 0x0 0x10000>;
- interrupts = <0 61 0x4>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- usb3-lpm-capable;
- snps,dis-u1u2-when-u3-quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- configure-gfladj;
- };
+ usb0: usb3@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ configure-gfladj;
+ };
+
+ usb1: usb3@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <0 61 0x4>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ configure-gfladj;
+ };
- usb2: usb3@3100000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <0 63 0x4>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- usb3-lpm-capable;
- snps,dis-u1u2-when-u3-quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- configure-gfladj;
+ usb2: usb3@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ configure-gfladj;
+ };
};
sata: sata@3200000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -624,40 +624,48 @@
<&clockgen 4 1>;
};
- usb0: usb@2f00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- snps,dis-u1u2-when-u3-quirk;
- };
+ usb_aux_bus: usb_aux_bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
- usb1: usb@3000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3000000 0x0 0x10000>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- snps,dis-u1u2-when-u3-quirk;
- };
+ usb0: usb@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
+ };
+
+ usb1: usb@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
+ };
- usb2: usb@3100000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- snps,dis-u1u2-when-u3-quirk;
+ usb2: usb@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
+ };
};
sata: sata@3200000 {

60
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@ -0,0 +1,60 @@
From 9c0090519c422600596a9d7c1e6e33a5268dfce4 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Thu, 2 Aug 2018 17:54:28 +0300
Subject: [PATCH] sdk: dts: ls104x: drop smmu from the sdk device trees
SMMU is not supported for the SDK version of the dpaa ethernet
drivers so remove the SMMU node from the device tree.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 14 ++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 14 ++++++++++++++
2 files changed, 28 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
@@ -64,6 +64,20 @@
&soc {
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
+
+pcie@3400000 {
+ /delete-property/ iommu-map;
+};
+
+pcie@3500000 {
+ /delete-property/ iommu-map;
+};
+
+pcie@3600000 {
+ /delete-property/ iommu-map;
+};
+
+/delete-node/ iommu@9000000;
};
&fman0 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
@@ -64,6 +64,20 @@
&soc {
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
+
+pcie@3400000 {
+ /delete-property/ iommu-map;
+};
+
+pcie@3500000 {
+ /delete-property/ iommu-map;
+};
+
+pcie@3600000 {
+ /delete-property/ iommu-map;
+};
+
+/delete-node/ iommu@9000000;
};
&fsldpaa {

41
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@ -0,0 +1,41 @@
From 5fb032ca86c078429ecdde3cbd9040702bb86954 Mon Sep 17 00:00:00 2001
From: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
Date: Fri, 20 Apr 2018 11:00:09 +0300
Subject: [PATCH] arm64: dts: lx2160a: add MDIO device-tree nodes
Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -478,6 +478,28 @@
little-endian;
};
+ /* TODO: WRIOP (CCSR?) */
+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8B96000 0x0 0x1000>;
+ device_type = "mdio"; /* TODO: is this necessary? */
+ little-endian; /* force the driver in LE mode */
+
+ /* Not necessary on the QDS, but needed on the RDB */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8B97000 0x0 0x1000>;
+ device_type = "mdio"; /* TODO: is this necessary? */
+ little-endian; /* force the driver in LE mode */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;

44
target/linux/layerscape/patches-5.4/302-dts-0021-arm64-dts-lx2160a-rdb-Add-RGMII-PHY-nodes-for-dpmac-.patch Normal file
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@ -0,0 +1,44 @@
From 08726d24b8552e4a986631090e063d38cd2d82cf Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Tue, 10 Jul 2018 13:56:56 +0300
Subject: [PATCH] arm64: dts: lx2160a-rdb: Add RGMII PHY nodes for dpmac 17 and
18
* Both are AR8035 chips
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 25 +++++++++++++++++++++++
1 file changed, 25 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -159,3 +159,28 @@
&usb1 {
status = "okay";
};
+
+&emdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x1>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+ rgmii_phy2: ethernet-phy@2 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x2>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+};
+
+&dpmac17 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&dpmac18 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-id";
+};

30
target/linux/layerscape/patches-5.4/302-dts-0022-arm64-dts-lx2160a-correct-scl-gpios-property.patch Normal file
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@ -0,0 +1,30 @@
From a99acc11751ea640c7687155e964612b232bc492 Mon Sep 17 00:00:00 2001
From: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Date: Mon, 29 Oct 2018 10:37:03 +0800
Subject: [PATCH] arm64: dts: lx2160a: correct scl-gpios property
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -508,7 +508,7 @@
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 15>;
- scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -553,7 +553,7 @@
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 15>;
- scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
status = "disabled";
};

62
target/linux/layerscape/patches-5.4/302-dts-0023-arm64-dts-lx2160a-add-dspi-controller-DT-nodes.patch Normal file
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@ -0,0 +1,62 @@
From df8cea437a14a4a412a32058ca49a2b30b48cc71 Mon Sep 17 00:00:00 2001
From: Chuanhua Han <chuanhua.han@nxp.com>
Date: Fri, 26 Oct 2018 12:08:55 +0800
Subject: [PATCH] arm64: dts: lx2160a: add dspi controller DT nodes
Add the dspi support on lx2160
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 39 ++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -603,6 +603,45 @@
status = "disabled";
};
+ dspi0: spi@2100000 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <0>;
+ status = "disabled";
+ };
+
+ dspi1: spi@2110000 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <1>;
+ status = "disabled";
+ };
+
+ dspi2: spi@2120000 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2120000 0x0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <2>;
+ status = "disabled";
+ };
+
esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;

59
target/linux/layerscape/patches-5.4/302-dts-0024-arm64-dts-lx2160a-add-DT-node-for-all-DSPI-controlle.patch Normal file
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@ -0,0 +1,59 @@
From 3f304579d634bcbef18fec939e407c8e789637c8 Mon Sep 17 00:00:00 2001
From: Chuanhua Han <chuanhua.han@nxp.com>
Date: Fri, 26 Oct 2018 12:11:25 +0800
Subject: [PATCH] arm64: dts: lx2160a: add DT node for all DSPI controller
Add device tree node for first flash (CS0) connected
to all dspi controller.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 36 +++++++++++++++++++++++
1 file changed, 36 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -35,6 +35,42 @@
status = "okay";
};
+&dspi0 {
+ status = "okay";
+
+ dflash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&dspi1 {
+ status = "okay";
+
+ dflash1: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&dspi2 {
+ status = "okay";
+
+ dflash2: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
&esdhc0 {
status = "okay";
};

745
target/linux/layerscape/patches-5.4/302-dts-0025-arm64-dts-nxp-ls208xa-add-more-thermal-zone-support.patch Normal file
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@ -0,0 +1,745 @@
From d05cf625f27335320a2ad883b7f7c4cd638dca99 Mon Sep 17 00:00:00 2001
From: Yuantian Tang <andy.tang@nxp.com>
Date: Mon, 5 Nov 2018 17:25:32 +0800
Subject: [PATCH] arm64: dts: nxp: ls208xa: add more thermal zone support
Ls208xa has several thermal sensors. Add all the sensor id to dts
to enable them.
To make the dts cleaner, re-organize the nodes to split out the
common part so that it can be shared with other SoCs.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 8 +-
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 8 +-
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 70 ++++---
arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi | 99 ++++++++++
arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi | 99 ++++++++++
arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi | 99 ++++++++++
arch/arm64/boot/dts/freescale/fsl-tmu.dtsi | 251 ++++++++++++++++++++++++
7 files changed, 590 insertions(+), 44 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -12,7 +12,7 @@
#include "fsl-ls208xa.dtsi"
&cpu {
- cpu0: cpu@0 {
+ cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
@@ -32,7 +32,7 @@
#cooling-cells = <2>;
};
- cpu2: cpu@100 {
+ cooling_map1: cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
@@ -52,7 +52,7 @@
#cooling-cells = <2>;
};
- cpu4: cpu@200 {
+ cooling_map2: cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
@@ -72,7 +72,7 @@
#cooling-cells = <2>;
};
- cpu6: cpu@300 {
+ cooling_map3: cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -12,7 +12,7 @@
#include "fsl-ls208xa.dtsi"
&cpu {
- cpu0: cpu@0 {
+ cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
@@ -32,7 +32,7 @@
#cooling-cells = <2>;
};
- cpu2: cpu@100 {
+ cooling_map1: cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
@@ -52,7 +52,7 @@
#cooling-cells = <2>;
};
- cpu4: cpu@200 {
+ cooling_map2: cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
@@ -72,7 +72,7 @@
#cooling-cells = <2>;
};
- cpu6: cpu@300 {
+ cooling_map3: cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x300>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -77,42 +77,7 @@
mask = <0x2>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
-
- thermal-sensors = <&tmu 4>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu-crit {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
+ #include "fsl-tmu.dtsi"
timer: timer {
compatible = "arm,armv8-timer";
@@ -907,3 +872,36 @@
};
};
};
+
+#include "fsl-tmu-map1.dtsi"
+#include "fsl-tmu-map2.dtsi"
+#include "fsl-tmu-map3.dtsi"
+&thermal_zones {
+ thermal-zone1 {
+ status = "okay";
+ };
+
+ thermal-zone2{
+ status = "okay";
+ };
+
+ thermal-zone3{
+ status = "okay";
+ };
+
+ thermal-zone4{
+ status = "okay";
+ };
+
+ thermal-zone5{
+ status = "okay";
+ };
+
+ thermal-zone6{
+ status = "okay";
+ };
+
+ thermal-zone7 {
+ status = "okay";
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Thermal Monitor Unit.
+ *
+ * Copyright 2018 NXP
+ *
+ * Tang Yuantian <andy.tang@nxp.com>
+ *
+ */
+
+&thermal_zones {
+ thermal-zone0 {
+ cooling-maps {
+ map1 {
+ trip = <&alert0>;
+ cooling-device =
+ <&cooling_map1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone1 {
+ cooling-maps {
+ map1 {
+ trip = <&alert1>;
+ cooling-device =
+ <&cooling_map1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone2 {
+ cooling-maps {
+ map1 {
+ trip = <&alert2>;
+ cooling-device =
+ <&cooling_map1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone3 {
+ cooling-maps {
+ map1 {
+ trip = <&alert3>;
+ cooling-device =
+ <&cooling_map1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone4 {
+ cooling-maps {
+ map1 {
+ trip = <&alert4>;
+ cooling-device =
+ <&cooling_map1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone5 {
+ cooling-maps {
+ map1 {
+ trip = <&alert5>;
+ cooling-device =
+ <&cooling_map1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone6 {
+ cooling-maps {
+ map1 {
+ trip = <&alert6>;
+ cooling-device =
+ <&cooling_map1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone7 {
+ cooling-maps {
+ map1 {
+ trip = <&alert7>;
+ cooling-device =
+ <&cooling_map1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Thermal Monitor Unit.
+ *
+ * Copyright 2018 NXP
+ *
+ * Tang Yuantian <andy.tang@nxp.com>
+ *
+ */
+
+&thermal_zones {
+ thermal-zone0 {
+ cooling-maps {
+ map2 {
+ trip = <&alert0>;
+ cooling-device =
+ <&cooling_map2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone1 {
+ cooling-maps {
+ map2 {
+ trip = <&alert1>;
+ cooling-device =
+ <&cooling_map2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone2 {
+ cooling-maps {
+ map2 {
+ trip = <&alert2>;
+ cooling-device =
+ <&cooling_map2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone3 {
+ cooling-maps {
+ map2 {
+ trip = <&alert3>;
+ cooling-device =
+ <&cooling_map2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone4 {
+ cooling-maps {
+ map2 {
+ trip = <&alert4>;
+ cooling-device =
+ <&cooling_map2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone5 {
+ cooling-maps {
+ map2 {
+ trip = <&alert5>;
+ cooling-device =
+ <&cooling_map2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone6 {
+ cooling-maps {
+ map2 {
+ trip = <&alert6>;
+ cooling-device =
+ <&cooling_map2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone7 {
+ cooling-maps {
+ map2 {
+ trip = <&alert7>;
+ cooling-device =
+ <&cooling_map2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Thermal Monitor Unit.
+ *
+ * Copyright 2018 NXP
+ *
+ * Tang Yuantian <andy.tang@nxp.com>
+ *
+ */
+
+&thermal_zones {
+ thermal-zone0 {
+ cooling-maps {
+ map3 {
+ trip = <&alert0>;
+ cooling-device =
+ <&cooling_map3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone1 {
+ cooling-maps {
+ map3 {
+ trip = <&alert1>;
+ cooling-device =
+ <&cooling_map3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone2 {
+ cooling-maps {
+ map3 {
+ trip = <&alert2>;
+ cooling-device =
+ <&cooling_map3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone3 {
+ cooling-maps {
+ map3 {
+ trip = <&alert3>;
+ cooling-device =
+ <&cooling_map3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone4 {
+ cooling-maps {
+ map3 {
+ trip = <&alert4>;
+ cooling-device =
+ <&cooling_map3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone5 {
+ cooling-maps {
+ map3 {
+ trip = <&alert5>;
+ cooling-device =
+ <&cooling_map3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone6 {
+ cooling-maps {
+ map3 {
+ trip = <&alert6>;
+ cooling-device =
+ <&cooling_map3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone7 {
+ cooling-maps {
+ map3 {
+ trip = <&alert7>;
+ cooling-device =
+ <&cooling_map3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Thermal Monitor Unit.
+ *
+ * Copyright 2018 NXP
+ *
+ * Tang Yuantian <andy.tang@nxp.com>
+ *
+ */
+
+thermal_zones: thermal-zones {
+ thermal_zone0: thermal-zone0 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+ status = "disabled";
+
+ trips {
+ alert0: alert0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit0: crit0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert0>;
+ cooling-device =
+ <&cooling_map0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone1 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 1>;
+ status = "disabled";
+
+ trips {
+ alert1: alert1 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit1: crit1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert1>;
+ cooling-device =
+ <&cooling_map0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone2 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 2>;
+ status = "disabled";
+
+ trips {
+ alert2: alert2 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit2: crit2 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert2>;
+ cooling-device =
+ <&cooling_map0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone3 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 3>;
+ status = "disabled";
+
+ trips {
+ alert3: alert3 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit3: crit3 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert3>;
+ cooling-device =
+ <&cooling_map0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone4 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 4>;
+ status = "disabled";
+
+ trips {
+ alert4: alert4 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit4: crit4 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert4>;
+ cooling-device =
+ <&cooling_map0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone5 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 5>;
+ status = "disabled";
+
+ trips {
+ alert5: alert5 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit5: crit5 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert5>;
+ cooling-device =
+ <&cooling_map0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone6 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 6>;
+ status = "disabled";
+
+ trips {
+ alert6: alert6 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit6: crit6 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert6>;
+ cooling-device =
+ <&cooling_map0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ thermal-zone7 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 7>;
+ status = "disabled";
+
+ trips {
+ alert7: alert7 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit7: crit7 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert7>;
+ cooling-device =
+ <&cooling_map0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};

314
target/linux/layerscape/patches-5.4/302-dts-0026-arm64-dts-nxp-add-more-thermal-zone-support.patch Normal file
View File

@ -0,0 +1,314 @@
From 314a3a062e5e8fe76b3c43a8731ffe4bd58bc1be Mon Sep 17 00:00:00 2001
From: Yuantian Tang <andy.tang@nxp.com>
Date: Mon, 5 Nov 2018 17:40:20 +0800
Subject: [PATCH] arm64: dts: nxp: add more thermal zone support
To enable all the supported thermal sensors, add sensor id information
to thermal zone node.
Dts for ls1012a, ls1046a, ls1043a, ls1088a are updated.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 39 ++++------------
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 61 ++++++++++++--------------
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 57 ++++++++++--------------
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 53 +++++++---------------
4 files changed, 75 insertions(+), 135 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -28,7 +28,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu0: cpu@0 {
+ cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@@ -100,36 +100,7 @@
mask = <0x02>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
- thermal-sensors = <&tmu 0>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
- };
- };
+ #include "fsl-tmu.dtsi"
soc {
compatible = "simple-bus";
@@ -572,3 +543,9 @@
};
};
};
+
+&thermal_zones {
+ thermal-zone0 {
+ status = "okay";
+ };
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -39,7 +39,7 @@
*
* Currently supported enable-method is psci v0.2
*/
- cpu0: cpu@0 {
+ cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@@ -148,38 +148,7 @@
mask = <0x02>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
-
- thermal-sensors = <&tmu 3>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
+ #include "fsl-tmu.dtsi"
timer {
compatible = "arm,armv8-timer";
@@ -915,3 +884,29 @@
#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"
+
+&thermal_zones {
+ thermal-zone0 {
+ status = "okay";
+ };
+
+ thermal-zone1 {
+ status = "okay";
+ };
+
+ thermal-zone2 {
+ status = "okay";
+ };
+
+ thermal-zone3 {
+ status = "okay";
+ };
+
+ thermal-zone4 {
+ status = "okay";
+ };
+
+ thermal-zone5 {
+ status = "okay";
+ };
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -34,7 +34,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu0: cpu@0 {
+ cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
@@ -116,38 +116,7 @@
mask = <0x02>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
- thermal-sensors = <&tmu 3>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
+ #include "fsl-tmu.dtsi"
timer {
compatible = "arm,armv8-timer";
@@ -882,3 +851,25 @@
#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"
+
+&thermal_zones {
+ thermal-zone0 {
+ status = "okay";
+ };
+
+ thermal-zone1 {
+ status = "okay";
+ };
+
+ thermal-zone2 {
+ status = "okay";
+ };
+
+ thermal-zone3 {
+ status = "okay";
+ };
+
+ thermal-zone4 {
+ status = "okay";
+ };
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -25,7 +25,7 @@
#size-cells = <0>;
/* We have 2 clusters having 4 Cortex-A53 cores each */
- cpu0: cpu@0 {
+ cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@@ -61,7 +61,7 @@
#cooling-cells = <2>;
};
- cpu4: cpu@100 {
+ cooling_map1: cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
@@ -128,42 +128,7 @@
};
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
- thermal-sensors = <&tmu 0>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
+ #include "fsl-tmu.dtsi"
timer {
compatible = "arm,armv8-timer";
@@ -879,3 +844,15 @@
};
};
};
+
+#include "fsl-tmu-map1.dtsi"
+
+&thermal_zones {
+ thermal-zone0 {
+ status = "okay";
+ };
+
+ thermal-zone1 {
+ status = "okay";
+ };
+};

40
target/linux/layerscape/patches-5.4/302-dts-0027-arm64-dts-lx2160a-rdb-Add-Inphi-PHY-node.patch Normal file
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@ -0,0 +1,40 @@
From 7ff4d2213c5b21008bebf43ae5a60b4275f91c55 Mon Sep 17 00:00:00 2001
From: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Date: Mon, 29 Oct 2018 18:41:07 +0200
Subject: [PATCH] arm64: dts: lx2160a-rdb: Add Inphi PHY node
DPMAC5 and DPMAC6 are connected to 25G Inphi PHY
Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -175,6 +175,23 @@
};
};
+&emdio2 {
+ inphi_phy: emdio2_phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ interrupts = <0 9 IRQ_TYPE_EDGE_FALLING>,
+ <0 10 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&dpmac5 {
+ phy-handle = <&inphi_phy>;
+};
+
+&dpmac6 {
+ phy-handle = <&inphi_phy>;
+};
+
&dpmac17 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";

51
target/linux/layerscape/patches-5.4/302-dts-0028-arm64-dts-lx2160a-rdb-Add-Aquantia-PHY-nodes.patch Normal file
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@ -0,0 +1,51 @@
From 917e2edbf55e5bc6c98802a610d8b7c05c4e9c78 Mon Sep 17 00:00:00 2001
From: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Date: Mon, 29 Oct 2018 18:54:05 +0200
Subject: [PATCH] arm64: dts: lx2160a-rdb: Add Aquantia PHY nodes
DPMAC3 and DPMAC4 are connected to 10G Aquantia PHYs
Signed-off-by: Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -173,6 +173,18 @@
reg = <0x2>;
/* Poll mode - no "interrupts" property defined */
};
+ aquantia_phy1: ethernet-phy@4 {
+ /* AQR107 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x4>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+ aquantia_phy2: ethernet-phy@5 {
+ /* AQR107 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x5>;
+ /* Poll mode - no "interrupts" property defined */
+ };
};
&emdio2 {
@@ -184,6 +196,16 @@
};
};
+&dpmac3 {
+ phy-handle = <&aquantia_phy1>;
+ phy-connection-type = "xgmii";
+};
+
+&dpmac4 {
+ phy-handle = <&aquantia_phy2>;
+ phy-connection-type = "xgmii";
+};
+
&dpmac5 {
phy-handle = <&inphi_phy>;
};

107
target/linux/layerscape/patches-5.4/302-dts-0029-arm64-dts-lx2160-Add-all-pcs-mdio-definitions-accord.patch Normal file
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@ -0,0 +1,107 @@
From 39c8c9b6e4db9694935fe4a856ea66ff36ace7d0 Mon Sep 17 00:00:00 2001
From: Florinel Iordache <florinel.iordache@nxp.com>
Date: Tue, 30 Oct 2018 09:42:39 +0200
Subject: [PATCH] arm64: dts: lx2160: Add all pcs mdio definitions according to
RM
This change is required in preparation for adding 40GBase-KR support in DTS for LX2160
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 85 ++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -500,6 +500,91 @@
#size-cells = <0>;
};
+ pcs_mdio1: mdio@0x8c07000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c07000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio2: mdio@0x8c0b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0b000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio3: mdio@0x8c0f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0f000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio4: mdio@0x8c13000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c13000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio5: mdio@0x8c17000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c17000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio6: mdio@0x8c1b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1b000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio7: mdio@0x8c1f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1f000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pcs_mdio8: mdio@0x8c23000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c23000 0x0 0x1000>;
+ device_type = "mdio";
+ little-endian;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serdes1: serdes@1ea0000 {
+ reg = <0x0 0x1ea0000 0 0x00002000>;
+ compatible = "fsl,serdes-28g";
+ };
+
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;

57
target/linux/layerscape/patches-5.4/302-dts-0030-arm64-dts-lx2160-PCS-PHY-definitions-for-10GBase-KR-.patch Normal file
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@ -0,0 +1,57 @@
From c1619d9de2da093a585426e9cef353ca1789236d Mon Sep 17 00:00:00 2001
From: Florinel Iordache <florinel.iordache@nxp.com>
Date: Mon, 5 Nov 2018 17:02:19 +0200
Subject: [PATCH] arm64: dts: lx2160: PCS PHY definitions for 10GBase-KR and
40GBase-KR backplane modes
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 40 +++++++++++++++++++++++
1 file changed, 40 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -162,3 +162,43 @@
&usb1 {
status = "okay";
};
+
+&pcs_mdio1 {
+ pcs_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ backplane-mode = "40gbase-kr";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */
+ };
+};
+
+&pcs_mdio2 {
+ pcs_phy2: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ backplane-mode = "40gbase-kr";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */
+ };
+};
+
+&pcs_mdio3 {
+ pcs_phy3: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ backplane-mode = "10gbase-kr";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0xF00 0x100>; /* lane H */
+ };
+};
+
+&pcs_mdio4 {
+ pcs_phy4: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ backplane-mode = "10gbase-kr";
+ reg = <0x0>;
+ fsl,lane-handle = <&serdes1>;
+ fsl,lane-reg = <0xE00 0x100>; /* lane G */
+ };
+};

39
target/linux/layerscape/patches-5.4/302-dts-0031-arm64-dts-lx2160-DPMAC-connections-to-backplane-PHYs.patch Normal file
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@ -0,0 +1,39 @@
From 01af235657e4d8f5f87b5e06bcf42baf53e1ff8d Mon Sep 17 00:00:00 2001
From: Florinel Iordache <florinel.iordache@nxp.com>
Date: Mon, 5 Nov 2018 17:03:04 +0200
Subject: [PATCH] arm64: dts: lx2160: DPMAC connections to backplane PHYs
example
This is an example of device tree nodes required to enable 10GBase-KR and 40GBase-KR on LX2160
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -202,3 +202,23 @@
fsl,lane-reg = <0xE00 0x100>; /* lane G */
};
};
+
+/* Update DPMAC connections to 40G backplane PHYs
+ * &dpmac1 {
+ * phy-handle = <&pcs_phy1>;
+ * };
+ *
+ * &dpmac2 {
+ * phy-handle = <&pcs_phy2>;
+ * };
+ */
+
+/* Update DPMAC connections to 10G backplane PHYs
+ * &dpmac3 {
+ * phy-handle = <&pcs_phy3>;
+ * };
+ *
+ * &dpmac4 {
+ * phy-handle = <&pcs_phy4>;
+ * };
+ */

53
target/linux/layerscape/patches-5.4/302-dts-0032-arm64-dts-Added-endianness-information-to-dts-serdes.patch Normal file
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@ -0,0 +1,53 @@
From d783144d6738af1d2ef3a91ef3cb2ef8529bb041 Mon Sep 17 00:00:00 2001
From: Florinel Iordache <florinel.iordache@nxp.com>
Date: Mon, 5 Nov 2018 17:04:05 +0200
Subject: [PATCH] arm64: dts: Added endianness information to dts serdes node
This change is required to specify that serdes HW peripheral is little-endian.
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -184,8 +184,9 @@
};
serdes1: serdes@1ea0000 {
- reg = <0x0 0x1ea0000 0 0x00002000>;
compatible = "fsl,serdes-10g";
+ reg = <0x0 0x1ea0000 0 0x00002000>;
+ little-endian;
};
tmu: tmu@1f80000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -834,8 +834,9 @@
};
serdes1: serdes@1ea0000 {
- reg = <0x0 0x1ea0000 0 0x00002000>;
compatible = "fsl,serdes-10g";
+ reg = <0x0 0x1ea0000 0 0x00002000>;
+ little-endian;
};
ccn@4000000 {
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -581,8 +581,9 @@
};
serdes1: serdes@1ea0000 {
- reg = <0x0 0x1ea0000 0 0x00002000>;
compatible = "fsl,serdes-28g";
+ reg = <0x0 0x1ea0000 0 0x00002000>;
+ little-endian;
};
i2c0: i2c@2000000 {

183
target/linux/layerscape/patches-5.4/302-dts-0033-arm64-dts-freescale-lx2160a-add-pcie-DT-nodes.patch Normal file
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@ -0,0 +1,183 @@
From 86e03654997db1b70e71f717ab3e74b1df2f402c Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Thu, 13 Jul 2017 18:28:27 +0800
Subject: [PATCH] arm64: dts: freescale: lx2160a: add pcie DT nodes
The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 162 +++++++++++++++++++++++++
1 file changed, 162 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -903,6 +903,168 @@
status = "disabled";
};
+ pcie@3400000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x88 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@3600000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x90 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@3700000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
+ 0x98 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@3800000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
+ 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@3900000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
+ 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;

29
target/linux/layerscape/patches-5.4/302-dts-0034-arm64-dts-freescale-lx2160a-Inphi-in112525_s03-mdio-.patch Normal file
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@ -0,0 +1,29 @@
From fa7b2d215b494f912b591f28c1205593bccfc2cc Mon Sep 17 00:00:00 2001
From: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Date: Sun, 16 Dec 2018 23:05:12 +0200
Subject: [PATCH] arm64: dts: freescale: lx2160a: Inphi in112525_s03 mdio node
Add Inphi retimer phyid in the mdio node, solving the probe issue
for this non-standard clause-45 device.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -188,11 +188,9 @@
};
&emdio2 {
- inphi_phy: emdio2_phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
+ inphi_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0210.7440";
reg = <0x0>;
- interrupts = <0 9 IRQ_TYPE_EDGE_FALLING>,
- <0 10 IRQ_TYPE_EDGE_FALLING>;
};
};

24
target/linux/layerscape/patches-5.4/302-dts-0035-arm64-dts-lx2160a-add-optee-tz-node.patch Normal file
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@ -0,0 +1,24 @@
From 9ab6cc70cd84ca4a140b30b8a0a2371a3585a72a Mon Sep 17 00:00:00 2001
From: Pankaj Gupta <pankaj.gupta@nxp.com>
Date: Tue, 27 Nov 2018 15:33:08 +0530
Subject: [PATCH] arm64: dts: lx2160a: add optee-tz node
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1287,4 +1287,11 @@
};
};
};
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
};

86
target/linux/layerscape/patches-5.4/302-dts-0036-arm64-dts-ls104x-constrain-sata-dma-address-size.patch Normal file
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@ -0,0 +1,86 @@
From 4a7dcac3fd18b182f882b65161267612713f72dc Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Tue, 11 Dec 2018 13:32:31 +0200
Subject: [PATCH] arm64: dts: ls104x: constrain sata dma address size
Limit the dma mask size for sata to 40 bits to match the actual address
size generated towards the interconnect. Re-use the already existing
auxiliary simple bus meant for usb but drop the usb reference from the
node name.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 18 +++++++++---------
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 18 +++++++++---------
2 files changed, 18 insertions(+), 18 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -695,7 +695,7 @@
<&clockgen 4 0>;
};
- usb_aux_bus: usb_aux_bus {
+ aux_bus: aux_bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
@@ -740,15 +740,15 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
configure-gfladj;
};
- };
- sata: sata@3200000 {
- compatible = "fsl,ls1043a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>,
- <0x0 0x20140520 0x0 0x4>;
- reg-names = "ahci", "sata-ecc";
- interrupts = <0 69 0x4>;
- clocks = <&clockgen 4 0>;
+ sata: sata@3200000 {
+ compatible = "fsl,ls1043a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <0 69 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
};
msi1: msi-controller1@1571000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -593,7 +593,7 @@
<&clockgen 4 1>;
};
- usb_aux_bus: usb_aux_bus {
+ aux_bus: aux_bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
@@ -635,15 +635,15 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
};
- };
- sata: sata@3200000 {
- compatible = "fsl,ls1046a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>,
- <0x0 0x20140520 0x0 0x4>;
- reg-names = "ahci", "sata-ecc";
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ sata: sata@3200000 {
+ compatible = "fsl,ls1046a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ };
};
msi1: msi-controller@1580000 {

37
target/linux/layerscape/patches-5.4/302-dts-0037-arm64-dts-lx2160a-qds-add-sata-node-support.patch Normal file
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@ -0,0 +1,37 @@
From 4551b9c547f7bf7b40d83f8762c77cee0041f5eb Mon Sep 17 00:00:00 2001
From: Peng Ma <peng.ma@nxp.com>
Date: Mon, 14 Jan 2019 08:26:40 +0000
Subject: [PATCH] arm64: dts: lx2160a-qds: add sata node support
Add sata node support and Enable sata support
Signed-off-by: Peng Ma <peng.ma@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -203,6 +203,22 @@
};
};
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
+
/* Update DPMAC connections to 40G backplane PHYs
* &dpmac1 {
* phy-handle = <&pcs_phy1>;

242
target/linux/layerscape/patches-5.4/302-dts-0038-arm64-dts-ls1012a-use-phy-handle-to-handle-phy-param.patch Normal file
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@ -0,0 +1,242 @@
From 203a34f815c7e9320140bb2259ae5884575f0658 Mon Sep 17 00:00:00 2001
From: Calvin Johnson <calvin.johnson@nxp.com>
Date: Tue, 20 Nov 2018 21:52:03 +0530
Subject: [PATCH] arm64: dts: ls1012a: use phy-handle to handle phy params
Replace properties "fsl,gemac-phy-id" and "fsl,pfe-phy-if-flags"
and use phy-handle instead.
Create mdio node with phy-handles defining PHYs available on the
mdio bus.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
---
.../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 25 +++++++++++++---------
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 23 +++++++++++---------
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 23 +++++++++++---------
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 25 +++++++++++++---------
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 22 ++++++++++---------
5 files changed, 68 insertions(+), 50 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
@@ -58,14 +58,9 @@
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,gemac-bus-id = <0x0>; /* BUS_ID */
- fsl,gemac-phy-id = <0x1>; /* PHY_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii-2500";
- fsl,pfe-phy-if-flags = <0x0>;
-
- mdio@0 {
- reg = <0x1>; /* enabled/disabled */
- };
+ phy-handle = <&sgmii_phy1>;
};
ethernet@1 {
@@ -74,13 +69,23 @@
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
- fsl,gemac-phy-id = < 0x2>; /* PHY_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii-2500";
- fsl,pfe-phy-if-flags = <0x0>;
+ phy-handle = <&sgmii_phy2>;
+ };
+
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ };
- mdio@0 {
- reg = <0x0>; /* enabled/disabled */
+ sgmii_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
};
};
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -90,14 +90,9 @@
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,gemac-bus-id = <0x0>; /* BUS_ID */
- fsl,gemac-phy-id = <0x2>; /* PHY_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
- fsl,pfe-phy-if-flags = <0x0>;
-
- mdio@0 {
- reg = <0x1>; /* enabled/disabled */
- };
+ phy-handle = <&sgmii_phy1>;
};
ethernet@1 {
@@ -106,13 +101,21 @@
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,gemac-bus-id = <0x1>; /* BUS_ID */
- fsl,gemac-phy-id = <0x1>; /* PHY_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
- fsl,pfe-phy-if-flags = <0x0>;
+ phy-handle = <&sgmii_phy2>;
+ };
+
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy1: ethernet-phy@2 {
+ reg = <0x2>;
+ };
- mdio@0 {
- reg = <0x0>; /* enabled/disabled */
+ sgmii_phy2: ethernet-phy@1 {
+ reg = <0x1>;
};
};
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
@@ -111,14 +111,9 @@
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,gemac-bus-id = <0x0>; /* BUS_ID */
- fsl,gemac-phy-id = <0x2>; /* PHY_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
- fsl,pfe-phy-if-flags = <0x0>;
-
- mdio@0 {
- reg = <0x1>; /* enabled/disabled */
- };
+ phy-handle = <&sgmii_phy1>;
};
ethernet@1 {
@@ -127,13 +122,21 @@
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,gemac-bus-id = <0x1>; /* BUS_ID */
- fsl,gemac-phy-id = <0x1>; /* PHY_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
- fsl,pfe-phy-if-flags = <0x0>;
+ phy-handle = <&sgmii_phy2>;
+ };
+
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy1: ethernet-phy@2 {
+ reg = <0x2>;
+ };
- mdio@0 {
- reg = <0x0>; /* enabled/disabled */
+ sgmii_phy2: ethernet-phy@1 {
+ reg = <0x1>;
};
};
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -148,14 +148,9 @@
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,gemac-bus-id = <0x0>; /* BUS_ID */
- fsl,gemac-phy-id = <0x1>; /* PHY_ID */
fsl,mdio-mux-val = <0x2>;
phy-mode = "sgmii-2500";
- fsl,pfe-phy-if-flags = <0x0>;
-
- mdio@0 {
- reg = <0x1>; /* enabled/disabled */
- };
+ phy-handle = <&sgmii_phy1>;
};
ethernet@1 {
@@ -164,13 +159,23 @@
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,gemac-bus-id = <0x1>; /* BUS_ID */
- fsl,gemac-phy-id = <0x2>; /* PHY_ID */
fsl,mdio-mux-val = <0x3>;
phy-mode = "sgmii-2500";
- fsl,pfe-phy-if-flags = <0x0>;
+ phy-handle = <&sgmii_phy2>;
+ };
+
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ };
- mdio@0 {
- reg = <0x0>; /* enabled/disabled */
+ sgmii_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
};
};
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -59,14 +59,9 @@
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
fsl,gemac-bus-id = <0x0>; /* BUS_ID */
- fsl,gemac-phy-id = <0x2>; /* PHY_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
- fsl,pfe-phy-if-flags = <0x0>;
-
- mdio@0 {
- reg = <0x1>; /* enabled/disabled */
- };
+ phy-handle = <&sgmii_phy>;
};
ethernet@1 {
@@ -75,13 +70,20 @@
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
- fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "rgmii-txid";
- fsl,pfe-phy-if-flags = <0x0>;
+ phy-handle = <&rgmii_phy>;
+ };
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy: ethernet-phy@2 {
+ reg = <0x2>;
+ };
- mdio@0 {
- reg = <0x0>; /* enabled/disabled */
+ rgmii_phy: ethernet-phy@1 {
+ reg = <0x1>;
};
};
};

98
target/linux/layerscape/patches-5.4/302-dts-0039-arm64-dts-ls1012a-remove-unused-gemac-bus-id.patch Normal file
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@ -0,0 +1,98 @@
From 4ae484235c6b0994e223e802b7fc465ce3b8c4ba Mon Sep 17 00:00:00 2001
From: Calvin Johnson <calvin.johnson@nxp.com>
Date: Thu, 3 Jan 2019 11:07:24 +0530
Subject: [PATCH] arm64: dts: ls1012a: remove unused gemac-bus-id
gemac-bus-id is unused property and is removed.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 2 --
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 2 --
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 1 -
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 2 --
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 2 --
5 files changed, 9 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
@@ -57,7 +57,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
- fsl,gemac-bus-id = <0x0>; /* BUS_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii-2500";
phy-handle = <&sgmii_phy1>;
@@ -68,7 +67,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
- fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii-2500";
phy-handle = <&sgmii_phy2>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -89,7 +89,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
- fsl,gemac-bus-id = <0x0>; /* BUS_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy1>;
@@ -100,7 +99,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
- fsl,gemac-bus-id = <0x1>; /* BUS_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy2>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
@@ -121,7 +121,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
- fsl,gemac-bus-id = <0x1>; /* BUS_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy2>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -147,7 +147,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
- fsl,gemac-bus-id = <0x0>; /* BUS_ID */
fsl,mdio-mux-val = <0x2>;
phy-mode = "sgmii-2500";
phy-handle = <&sgmii_phy1>;
@@ -158,7 +157,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
- fsl,gemac-bus-id = <0x1>; /* BUS_ID */
fsl,mdio-mux-val = <0x3>;
phy-mode = "sgmii-2500";
phy-handle = <&sgmii_phy2>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -58,7 +58,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>; /* GEM_ID */
- fsl,gemac-bus-id = <0x0>; /* BUS_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "sgmii";
phy-handle = <&sgmii_phy>;
@@ -69,7 +68,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>; /* GEM_ID */
- fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
fsl,mdio-mux-val = <0x0>;
phy-mode = "rgmii-txid";
phy-handle = <&rgmii_phy>;

132
target/linux/layerscape/patches-5.4/302-dts-0040-arm64-dts-ls1012a-reorganize-pfe_mac-nodes.patch Normal file
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@ -0,0 +1,132 @@
From 4ed0fefb58b5788368fea2c69d646ee4f2e9e012 Mon Sep 17 00:00:00 2001
From: Calvin Johnson <calvin.johnson@nxp.com>
Date: Mon, 10 Dec 2018 10:03:51 +0530
Subject: [PATCH] arm64: dts: ls1012a: reorganize pfe_mac nodes
To keep platform specific properties in the platform dts files,
remove pfe_mac nodes from dtsi and define them in dts files.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 4 ++--
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 4 ++--
arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 4 ++--
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 4 ++--
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 4 ++--
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 5 -----
6 files changed, 10 insertions(+), 15 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
@@ -52,7 +52,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet@0 {
+ pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
@@ -62,7 +62,7 @@
phy-handle = <&sgmii_phy1>;
};
- ethernet@1 {
+ pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -84,7 +84,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet@0 {
+ pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
@@ -94,7 +94,7 @@
phy-handle = <&sgmii_phy1>;
};
- ethernet@1 {
+ pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
@@ -105,7 +105,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet@0 {
+ pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
@@ -116,7 +116,7 @@
phy-handle = <&sgmii_phy1>;
};
- ethernet@1 {
+ pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -142,7 +142,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet@0 {
+ pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
@@ -152,7 +152,7 @@
phy-handle = <&sgmii_phy1>;
};
- ethernet@1 {
+ pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -53,7 +53,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet@0 {
+ pfe_mac0: ethernet@0 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
@@ -63,7 +63,7 @@
phy-handle = <&sgmii_phy>;
};
- ethernet@1 {
+ pfe_mac1: ethernet@1 {
compatible = "fsl,pfe-gemac-port";
#address-cells = <1>;
#size-cells = <0>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -529,11 +529,6 @@
clock-names = "pfe";
status = "okay";
- pfe_mac0: ethernet@0 {
- };
-
- pfe_mac1: ethernet@1 {
- };
};
firmware {

109
target/linux/layerscape/patches-5.4/302-dts-0041-sdk-dts-ls104x-drop-smmu-from-the-qds-and-usdpaa-sdk.patch Normal file
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@ -0,0 +1,109 @@
From 6119ca5f113320d848ead38b141238b013f538c6 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Wed, 23 Jan 2019 16:28:36 +0200
Subject: [PATCH] sdk: dts: ls104x: drop smmu from the qds and usdpaa sdk dts
Also drop the smmu from the qds and usdpaa versions of the
SDK device trees because SMMU is supported only for the
upstream version of the dpaa ethernet drivers.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 14 ++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 14 ++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 14 ++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 14 ++++++++++++++
4 files changed, 56 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
@@ -64,6 +64,20 @@
&soc {
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
+
+pcie@3400000 {
+ /delete-property/ iommu-map;
+};
+
+pcie@3500000 {
+ /delete-property/ iommu-map;
+};
+
+pcie@3600000 {
+ /delete-property/ iommu-map;
+};
+
+/delete-node/ iommu@9000000;
};
&fman0 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
@@ -92,6 +92,20 @@
fsl,fman-oh-port = <&fman0_oh2>;
};
};
+
+ pcie@3400000 {
+ /delete-property/ iommu-map;
+ };
+
+ pcie@3500000 {
+ /delete-property/ iommu-map;
+ };
+
+ pcie@3600000 {
+ /delete-property/ iommu-map;
+ };
+
+ /delete-node/ iommu@9000000;
};
/ {
reserved-memory {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
@@ -64,6 +64,20 @@
&soc {
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
+
+pcie@3400000 {
+ /delete-property/ iommu-map;
+};
+
+pcie@3500000 {
+ /delete-property/ iommu-map;
+};
+
+pcie@3600000 {
+ /delete-property/ iommu-map;
+};
+
+/delete-node/ iommu@9000000;
};
&fsldpaa {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
@@ -85,6 +85,20 @@
fsl,fman-oh-port = <&fman0_oh2>;
};
};
+
+ pcie@3400000 {
+ /delete-property/ iommu-map;
+ };
+
+ pcie@3500000 {
+ /delete-property/ iommu-map;
+ };
+
+ pcie@3600000 {
+ /delete-property/ iommu-map;
+ };
+
+ /delete-node/ iommu@9000000;
};
/ {
reserved-memory {

42
target/linux/layerscape/patches-5.4/302-dts-0042-arm64-dts-fix-the-LS104x-QDS-mdio-mux-support.patch Normal file
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@ -0,0 +1,42 @@
From 3c6ae8f4d45701683e671ea34bdddd0bf3e37a4d Mon Sep 17 00:00:00 2001
From: Camelia Groza <camelia.groza@nxp.com>
Date: Wed, 13 Feb 2019 17:52:00 +0200
Subject: [PATCH] arm64: dts: fix the LS104x QDS mdio-mux support
Set the "simple-bus" compatible and the fpga ranges in order to
successfully probe the mdio-mux-emi1.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 3 ++-
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -78,10 +78,11 @@
};
fpga: board-control@2,0 {
- compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
+ compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
reg = <0x2 0x0 0x0000100>;
#address-cells = <1>;
#size-cells = <1>;
+ ranges = <0 2 0 0x100>;
};
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -167,8 +167,9 @@
};
fpga: board-control@2,0 {
- compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
+ compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
reg = <0x2 0x0 0x0000100>;
+ ranges = <0 2 0 0x100>;
};
};

247
target/linux/layerscape/patches-5.4/302-dts-0043-arm64-dts-lx2160aqds-Add-mdio-mux-nodes.patch Normal file
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@ -0,0 +1,247 @@
From c9be87f17c64d08c06e4858589a0014f73868867 Mon Sep 17 00:00:00 2001
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Thu, 28 Feb 2019 17:28:36 +0530
Subject: [PATCH] arm64: dts: lx2160aqds: Add mdio mux nodes
The two external MDIO buses used to communicate with phy devices that are
external to SOC are muxed in LX2160AQDS board.
These buses can be routed to any one of the eight IO slots on LX2160AQDS
board depending on value in fpga register 0x54.
Additionally the external MDIO1 is used to communicate to the onboard
RGMII phy devices.
The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is
controlled by bits 4-7 of fpga register.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 8 ++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++--
3 files changed, 165 insertions(+), 12 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -29,6 +29,130 @@
regulator-boot-on;
regulator-always-on;
};
+
+ mdio-mux-1 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 0>;
+ mdio-parent-bus = <&emdio1>;
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ mdio@0 { /* On-board PHY #1 RGMI1*/
+ reg = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@8 { /* On-board PHY #2 RGMI2*/
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@18 { /* Slot #1 */
+ reg = <0x18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@19 { /* Slot #2 */
+ reg = <0x19>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1a { /* Slot #3 */
+ reg = <0x1a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1b { /* Slot #4 */
+ reg = <0x1b>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1c { /* Slot #5 */
+ reg = <0x1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1d { /* Slot #6 */
+ reg = <0x1d>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1e { /* Slot #7 */
+ reg = <0x1e>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1f { /* Slot #8 */
+ reg = <0x1f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio-mux-2 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 1>;
+ mdio-parent-bus = <&emdio2>;
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ mdio@0 { /* Slot #1 (secondary EMI) */
+ reg = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1 { /* Slot #2 (secondary EMI) */
+ reg = <0x01>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@2 { /* Slot #3 (secondary EMI) */
+ reg = <0x02>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@3 { /* Slot #4 (secondary EMI) */
+ reg = <0x03>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@4 { /* Slot #5 (secondary EMI) */
+ reg = <0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@5 { /* Slot #6 (secondary EMI) */
+ reg = <0x05>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@6 { /* Slot #7 (secondary EMI) */
+ reg = <0x06>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@7 { /* Slot #8 (secondary EMI) */
+ reg = <0x07>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
&crypto {
@@ -71,6 +195,14 @@
};
};
+&emdio1 {
+ status = "okay";
+};
+
+&emdio2 {
+ status = "okay";
+};
+
&esdhc0 {
status = "okay";
};
@@ -82,6 +214,19 @@
&i2c0 {
status = "okay";
+ fpga@66 {
+ compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
+ "simple-mfd";
+ reg = <0x66>;
+
+ mux: mux-controller {
+ compatible = "reg-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
+ <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
+ };
+ };
+
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -35,6 +35,14 @@
status = "okay";
};
+&emdio1 {
+ status = "okay";
+};
+
+&emdio2 {
+ status = "okay";
+};
+
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -478,26 +478,26 @@
little-endian;
};
- /* TODO: WRIOP (CCSR?) */
- emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
+ /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
+ emdio1: mdio@8b96000 {
compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8B96000 0x0 0x1000>;
- device_type = "mdio"; /* TODO: is this necessary? */
- little-endian; /* force the driver in LE mode */
-
- /* Not necessary on the QDS, but needed on the RDB */
+ reg = <0x0 0x8b96000 0x0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ little-endian; /* force the driver in LE mode */
+ status = "disabled";
};
- emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
+ /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
+ emdio2: mdio@8b97000 {
compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8B97000 0x0 0x1000>;
- device_type = "mdio"; /* TODO: is this necessary? */
- little-endian; /* force the driver in LE mode */
-
+ reg = <0x0 0x8b97000 0x0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ little-endian; /* force the driver in LE mode */
+ status = "disabled";
};
pcs_mdio1: mdio@0x8c07000 {

56
target/linux/layerscape/patches-5.4/302-dts-0044-sdk-arm64-dts-reduce-usdpaa-memory-to-4K-for-LS1046-.patch Normal file
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@ -0,0 +1,56 @@
From 97b563d9c0cf09897c1e7b793ef0fe677c66269a Mon Sep 17 00:00:00 2001
From: Nipun Gupta <nipun.gupta@nxp.com>
Date: Wed, 30 Jan 2019 19:18:13 +0530
Subject: [PATCH] sdk: arm64: dts: reduce usdpaa memory to 4K for LS1046/43
This patch reducing the USDPAA reseved memory to 4K.
In case USDPAA is to be used, 256MB needs to be reserved in the DTS file.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 9 +++++++--
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 9 +++++++--
2 files changed, 14 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
@@ -113,11 +113,16 @@
#size-cells = <2>;
ranges;
+ /* For legacy usdpaa based use-cases, update the size and
+ alignment parameters. e.g. to allocate 256 MB memory:
+ size = <0 0x10000000>;
+ alignment = <0 0x10000000>;
+ */
usdpaa_mem: usdpaa_mem {
compatible = "fsl,usdpaa-mem";
alloc-ranges = <0 0 0x10000 0>;
- size = <0 0x10000000>;
- alignment = <0 0x10000000>;
+ size = <0 0x1000>;
+ alignment = <0 0x1000>;
};
};
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
@@ -106,11 +106,16 @@
#size-cells = <2>;
ranges;
+ /* For legacy usdpaa based use-cases, update the size and
+ alignment parameters. e.g. to allocate 256 MB memory:
+ size = <0 0x10000000>;
+ alignment = <0 0x10000000>;
+ */
usdpaa_mem: usdpaa_mem {
compatible = "fsl,usdpaa-mem";
alloc-ranges = <0 0 0x10000 0>;
- size = <0 0x10000000>;
- alignment = <0 0x10000000>;
+ size = <0 0x1000>;
+ alignment = <0 0x1000>;
};
};
};

134
target/linux/layerscape/patches-5.4/302-dts-0045-arm64-dts-Fix-DWC3-IP-VBUS-glitch-issue-on-Layerscap.patch Normal file
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@ -0,0 +1,134 @@
From 0c7e3f6f557c2a68527980e940e6a605da1f9e12 Mon Sep 17 00:00:00 2001
From: Ran Wang <ran.wang_1@nxp.com>
Date: Wed, 16 Jan 2019 15:40:33 +0800
Subject: [PATCH] arm64: dts: Fix DWC3 IP VBUS glitch issue on Layerscape
platforms
Cover LS1012A, LS1043A, LS1046A, LS1088A, LS208xA, LX2160A
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 ++
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 ++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
6 files changed, 13 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -442,6 +442,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
};
sata: sata@3200000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -712,6 +712,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
configure-gfladj;
};
@@ -725,6 +726,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
configure-gfladj;
};
@@ -738,6 +740,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
configure-gfladj;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -610,6 +610,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
+ snps,host-vbus-glitches;
};
usb1: usb@3000000 {
@@ -622,6 +623,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
+ snps,host-vbus-glitches;
};
usb2: usb@3100000 {
@@ -634,6 +636,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
+ snps,host-vbus-glitches;
};
sata: sata@3200000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -452,6 +452,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
status = "disabled";
};
@@ -463,6 +464,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
status = "disabled";
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -820,6 +820,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
};
usb1: usb3@3110000 {
@@ -831,6 +832,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
};
serdes1: serdes@1ea0000 {
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -845,6 +845,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
status = "disabled";
};
@@ -856,6 +857,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
status = "disabled";
};

20
target/linux/layerscape/patches-5.4/302-dts-0046-ARM-dts-Fix-DWC3-IP-VBUS-glitch-issue-on-LS1021A.patch Normal file
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@ -0,0 +1,20 @@
From 3c1991fe18bca459d07dd78a2268e26008707f00 Mon Sep 17 00:00:00 2001
From: Ran Wang <ran.wang_1@nxp.com>
Date: Mon, 25 Feb 2019 13:38:01 +0800
Subject: [PATCH] ARM: dts: Fix DWC3 IP VBUS glitch issue on LS1021A
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -877,6 +877,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ snps,host-vbus-glitches;
};
pcie@3400000 {

25
target/linux/layerscape/patches-5.4/302-dts-0047-ARM-dts-ls1021aqds-enable-esdhc-controller.patch Normal file
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@ -0,0 +1,25 @@
From 6c3655acaa5766efe81f60ac6d428b0d184daa0d Mon Sep 17 00:00:00 2001
From: Yinbo Zhu <yinbo.zhu@nxp.com>
Date: Fri, 21 Dec 2018 11:38:44 +0800
Subject: [PATCH] ARM: dts: ls1021aqds: enable esdhc controller
This patch is to enable esdhc controller in ls1021aqds
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
arch/arm/boot/dts/ls1021a-qds.dts | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -165,6 +165,10 @@
status = "okay";
};
+&esdhc {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";

112
target/linux/layerscape/patches-5.4/302-dts-0048-arm64-dts-freescale-lx2160a-add-pcie-EP-mode-DT-node.patch Normal file
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@ -0,0 +1,112 @@
From 4de7a5e35eff9216fa5e6b138b0ffa75e045e397 Mon Sep 17 00:00:00 2001
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Date: Thu, 28 Feb 2019 14:09:01 +0800
Subject: [PATCH] arm64: dts: freescale: lx2160a: add pcie EP mode DT nodes
The LX2160A PCIe EP mode node.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 56 ++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -932,6 +932,15 @@
status = "disabled";
};
+ pcie_ep@3400000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ status = "disabled";
+ };
+
pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -959,6 +968,15 @@
status = "disabled";
};
+ pcie_ep@3500000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ status = "disabled";
+ };
+
pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -986,6 +1004,16 @@
status = "disabled";
};
+ pcie_ep@3600000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x90 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ max-functions = <2>;
+ status = "disabled";
+ };
+
pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
@@ -1013,6 +1041,15 @@
status = "disabled";
};
+ pcie_ep@3700000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03700000 0x0 0x00100000
+ 0x98 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ status = "disabled";
+ };
+
pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
@@ -1040,6 +1077,16 @@
status = "disabled";
};
+ pcie_ep@3800000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03800000 0x0 0x00100000
+ 0xa0 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ max-functions = <2>;
+ status = "disabled";
+ };
+
pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
@@ -1067,6 +1114,15 @@
status = "disabled";
};
+ pcie_ep@3900000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03900000 0x0 0x00100000
+ 0xa8 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;

879
target/linux/layerscape/patches-5.4/302-dts-0049-sdk-dts-ls104x-move-dma-coherent-from-soc-to-its-chi.patch Normal file
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@ -0,0 +1,879 @@
From 6795bab4281aa9ed8e0ba3fbba06de8dd369b17c Mon Sep 17 00:00:00 2001
From: Ran Wang <ran.wang_1@nxp.com>
Date: Thu, 21 Feb 2019 13:32:59 +0800
Subject: [PATCH] sdk: dts: ls104x move dma-coherent from soc to its child
nodes
Since SMMU is not supported for SDK version, USB function will down if
still apply property 'dma-coherent' in scope of soc (USB driver is not
ready to support it alone) in SDK device trees, decide to remove it.
And add dma-coherent on other non-USB child nodes under soc.
dma-coherent feature in dts node will cause issue that
QE-HDLC received too little, when a lot of data is transmitted while
just little data received, the Tx buffer will run out.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
.../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 184 ++++++++++++++++++++-
.../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 177 ++++++++++++++++++++
.../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 4 +
.../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 175 ++++++++++++++++++++
.../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 178 ++++++++++++++++++++
.../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 4 +
6 files changed, 719 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
@@ -62,19 +62,24 @@
};
&soc {
+/delete-property/ dma-coherent;
+
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
pcie@3400000 {
- /delete-property/ iommu-map;
+ /delete-property/ iommu-map;
+ dma-coherent;
};
pcie@3500000 {
- /delete-property/ iommu-map;
+ /delete-property/ iommu-map;
+ dma-coherent;
};
pcie@3600000 {
- /delete-property/ iommu-map;
+ /delete-property/ iommu-map;
+ dma-coherent;
};
/delete-node/ iommu@9000000;
@@ -82,4 +87,177 @@ pcie@3600000 {
&fman0 {
compatible = "fsl,fman", "simple-bus";
+ dma-coherent;
+};
+
+&clockgen {
+ dma-coherent;
+};
+
+&scfg {
+ dma-coherent;
+};
+
+&crypto {
+ dma-coherent;
+};
+
+&dcfg {
+ dma-coherent;
+};
+
+&ifc {
+ dma-coherent;
+};
+
+&qspi {
+ dma-coherent;
+};
+
+&esdhc {
+ dma-coherent;
+};
+
+&ddr {
+ dma-coherent;
+};
+
+&tmu {
+ dma-coherent;
+};
+
+&qman {
+ dma-coherent;
+};
+
+&bman {
+ dma-coherent;
+};
+
+&bportals {
+ dma-coherent;
+};
+
+&qportals {
+ dma-coherent;
+};
+
+&dspi0 {
+ dma-coherent;
+};
+
+&dspi1 {
+ dma-coherent;
+};
+
+&i2c0 {
+ dma-coherent;
+};
+
+&i2c1 {
+ dma-coherent;
+};
+
+&i2c2 {
+ dma-coherent;
+};
+
+&i2c3 {
+ dma-coherent;
+};
+
+&duart0 {
+ dma-coherent;
+};
+
+&duart1 {
+ dma-coherent;
+};
+
+&duart2 {
+ dma-coherent;
+};
+
+&duart3 {
+ dma-coherent;
+};
+
+&gpio1 {
+ dma-coherent;
+};
+
+&gpio2 {
+ dma-coherent;
+};
+
+&gpio3 {
+ dma-coherent;
+};
+
+&gpio4 {
+ dma-coherent;
+};
+
+&uqe {
+ dma-coherent;
+};
+
+&lpuart0 {
+ dma-coherent;
+};
+
+&lpuart1 {
+ dma-coherent;
+};
+
+&lpuart2 {
+ dma-coherent;
+};
+
+&lpuart3 {
+ dma-coherent;
+};
+
+&lpuart4 {
+ dma-coherent;
+};
+
+&lpuart5 {
+ dma-coherent;
+};
+
+&ftm0 {
+ dma-coherent;
+};
+
+&wdog0 {
+ dma-coherent;
+};
+
+&edma0 {
+ dma-coherent;
+};
+
+&qdma {
+ dma-coherent;
+};
+
+&msi1 {
+ dma-coherent;
+};
+
+&msi2 {
+ dma-coherent;
+};
+
+&msi3 {
+ dma-coherent;
+};
+
+&ptp_timer0 {
+ dma-coherent;
+};
+
+&fsldpaa {
+ dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
@@ -62,19 +62,24 @@
};
&soc {
+/delete-property/ dma-coherent;
+
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
pcie@3400000 {
/delete-property/ iommu-map;
+ dma-coherent;
};
pcie@3500000 {
/delete-property/ iommu-map;
+ dma-coherent;
};
pcie@3600000 {
/delete-property/ iommu-map;
+ dma-coherent;
};
/delete-node/ iommu@9000000;
@@ -83,3 +88,175 @@ pcie@3600000 {
&fman0 {
compatible = "fsl,fman", "simple-bus";
};
+
+&clockgen {
+ dma-coherent;
+};
+
+&scfg {
+ dma-coherent;
+};
+
+&crypto {
+ dma-coherent;
+};
+
+&dcfg {
+ dma-coherent;
+};
+
+&ifc {
+ dma-coherent;
+};
+
+&qspi {
+ dma-coherent;
+};
+
+&esdhc {
+ dma-coherent;
+};
+
+&ddr {
+ dma-coherent;
+};
+
+&tmu {
+ dma-coherent;
+};
+
+&qman {
+ dma-coherent;
+};
+
+&bman {
+ dma-coherent;
+};
+
+&bportals {
+ dma-coherent;
+};
+
+&qportals {
+ dma-coherent;
+};
+
+&dspi0 {
+ dma-coherent;
+};
+
+&dspi1 {
+ dma-coherent;
+};
+
+&i2c0 {
+ dma-coherent;
+};
+
+&i2c1 {
+ dma-coherent;
+};
+
+&i2c2 {
+ dma-coherent;
+};
+
+&i2c3 {
+ dma-coherent;
+};
+
+&duart0 {
+ dma-coherent;
+};
+
+&duart1 {
+ dma-coherent;
+};
+
+&duart2 {
+ dma-coherent;
+};
+
+&duart3 {
+ dma-coherent;
+};
+
+&gpio1 {
+ dma-coherent;
+};
+
+&gpio2 {
+ dma-coherent;
+};
+
+&gpio3 {
+ dma-coherent;
+};
+
+&gpio4 {
+ dma-coherent;
+};
+
+&lpuart0 {
+ dma-coherent;
+};
+
+&lpuart1 {
+ dma-coherent;
+};
+
+&lpuart2 {
+ dma-coherent;
+};
+
+&lpuart3 {
+ dma-coherent;
+};
+
+&lpuart4 {
+ dma-coherent;
+};
+
+&lpuart5 {
+ dma-coherent;
+};
+
+&ftm0 {
+ dma-coherent;
+};
+
+&wdog0 {
+ dma-coherent;
+};
+
+&edma0 {
+ dma-coherent;
+};
+
+&qdma {
+ dma-coherent;
+};
+
+&msi1 {
+ dma-coherent;
+};
+
+&msi2 {
+ dma-coherent;
+};
+
+&msi3 {
+ dma-coherent;
+};
+
+&fman0 {
+ dma-coherent;
+};
+
+&ptp_timer0 {
+ dma-coherent;
+};
+
+&fsldpaa {
+ dma-coherent;
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
@@ -16,6 +16,7 @@
fsl,bpid = <7>;
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
+ dma-coherent;
};
bp8: buffer-pool@8 {
@@ -23,6 +24,7 @@
fsl,bpid = <8>;
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ dma-coherent;
};
bp9: buffer-pool@9 {
@@ -30,10 +32,12 @@
fsl,bpid = <9>;
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ dma-coherent;
};
fsl,dpaa {
compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
+ dma-coherent;
ethernet@0 {
compatible = "fsl,dpa-ethernet-init";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
@@ -62,6 +62,8 @@
};
&soc {
+/delete-property/ dma-coherent;
+
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
@@ -90,4 +92,177 @@ pcie@3600000 {
&fman0 {
compatible = "fsl,fman", "simple-bus";
+ dma-coherent;
+};
+
+&clockgen {
+ dma-coherent;
+};
+
+&scfg {
+ dma-coherent;
+};
+
+&crypto {
+ dma-coherent;
+};
+
+&dcfg {
+ dma-coherent;
+};
+
+&ifc {
+ dma-coherent;
+};
+
+&qspi {
+ dma-coherent;
+};
+
+&esdhc {
+ dma-coherent;
+};
+
+&ddr {
+ dma-coherent;
+};
+
+&tmu {
+ dma-coherent;
+};
+
+&qman {
+ dma-coherent;
+};
+
+&bman {
+ dma-coherent;
+};
+
+&bportals {
+ dma-coherent;
+};
+
+&qportals {
+ dma-coherent;
+};
+
+&dspi {
+ dma-coherent;
+};
+
+&i2c0 {
+ dma-coherent;
+};
+
+&i2c1 {
+ dma-coherent;
+};
+
+&i2c2 {
+ dma-coherent;
+};
+
+&i2c3 {
+ dma-coherent;
+};
+
+&duart0 {
+ dma-coherent;
+};
+
+&duart1 {
+ dma-coherent;
+};
+
+&duart2 {
+ dma-coherent;
+};
+
+&duart3 {
+ dma-coherent;
+};
+
+&gpio0 {
+ dma-coherent;
+};
+
+&gpio1 {
+ dma-coherent;
+};
+
+&gpio2 {
+ dma-coherent;
+};
+
+&gpio3 {
+ dma-coherent;
+};
+
+&lpuart0 {
+ dma-coherent;
+};
+
+&lpuart1 {
+ dma-coherent;
+};
+
+&lpuart2 {
+ dma-coherent;
+};
+
+&lpuart3 {
+ dma-coherent;
+};
+
+&lpuart4 {
+ dma-coherent;
+};
+
+&lpuart5 {
+ dma-coherent;
+};
+
+&ftm0 {
+ dma-coherent;
+};
+
+&wdog0 {
+ dma-coherent;
+};
+
+&edma0 {
+ dma-coherent;
+};
+
+&sata {
+ dma-coherent;
+};
+
+&qdma {
+ dma-coherent;
+};
+
+&msi1 {
+ dma-coherent;
+};
+
+&msi2 {
+ dma-coherent;
+};
+
+&msi3 {
+ dma-coherent;
+};
+
+&ptp_timer0 {
+ dma-coherent;
+};
+
+&serdes1 {
+ dma-coherent;
+};
+
+&fsldpaa {
+ dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
@@ -62,6 +62,8 @@
};
&soc {
+/delete-property/ dma-coherent;
+
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
@@ -127,3 +129,179 @@ pcie@3600000 {
* phy-handle = <&pcsphy7>;
*};
*/
+
+&clockgen {
+ dma-coherent;
+};
+
+&scfg {
+ dma-coherent;
+};
+
+&crypto {
+ dma-coherent;
+};
+
+&dcfg {
+ dma-coherent;
+};
+
+&ifc {
+ dma-coherent;
+};
+
+&qspi {
+ dma-coherent;
+};
+
+&esdhc {
+ dma-coherent;
+};
+
+&ddr {
+ dma-coherent;
+};
+
+&tmu {
+ dma-coherent;
+};
+
+&qman {
+ dma-coherent;
+};
+
+&bman {
+ dma-coherent;
+};
+
+&bportals {
+ dma-coherent;
+};
+
+&qportals {
+ dma-coherent;
+};
+
+&dspi {
+ dma-coherent;
+};
+
+&i2c0 {
+ dma-coherent;
+};
+
+&i2c1 {
+ dma-coherent;
+};
+
+&i2c2 {
+ dma-coherent;
+};
+
+&i2c3 {
+ dma-coherent;
+};
+
+&duart0 {
+ dma-coherent;
+};
+
+&duart1 {
+ dma-coherent;
+};
+
+&duart2 {
+ dma-coherent;
+};
+
+&duart3 {
+ dma-coherent;
+};
+
+&gpio0 {
+ dma-coherent;
+};
+
+&gpio1 {
+ dma-coherent;
+};
+
+&gpio2 {
+ dma-coherent;
+};
+
+&gpio3 {
+ dma-coherent;
+};
+
+&lpuart0 {
+ dma-coherent;
+};
+
+&lpuart1 {
+ dma-coherent;
+};
+
+&lpuart2 {
+ dma-coherent;
+};
+
+&lpuart3 {
+ dma-coherent;
+};
+
+&lpuart4 {
+ dma-coherent;
+};
+
+&lpuart5 {
+ dma-coherent;
+};
+
+&ftm0 {
+ dma-coherent;
+};
+
+&wdog0 {
+ dma-coherent;
+};
+
+&edma0 {
+ dma-coherent;
+};
+
+&sata {
+ dma-coherent;
+};
+
+&qdma {
+ dma-coherent;
+};
+
+&msi1 {
+ dma-coherent;
+};
+
+&msi2 {
+ dma-coherent;
+};
+
+&msi3 {
+ dma-coherent;
+};
+
+&fman0 {
+ dma-coherent;
+};
+
+&ptp_timer0 {
+ dma-coherent;
+};
+
+&serdes1 {
+ dma-coherent;
+};
+
+&fsldpaa {
+ dma-coherent;
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
@@ -16,6 +16,7 @@
fsl,bpid = <7>;
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
+ dma-coherent;
};
bp8: buffer-pool@8 {
@@ -23,6 +24,7 @@
fsl,bpid = <8>;
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ dma-coherent;
};
bp9: buffer-pool@9 {
@@ -30,10 +32,12 @@
fsl,bpid = <9>;
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ dma-coherent;
};
fsl,dpaa {
compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
+ dma-coherent;
ethernet@2 {
compatible = "fsl,dpa-ethernet-init";

32
target/linux/layerscape/patches-5.4/302-dts-0050-arm64-dts-lx2160a-add-interrupt-property-for-aquanti.patch Normal file
View File

@ -0,0 +1,32 @@
From e260d97c7875d5ef6aca11e49bf2784966a877c2 Mon Sep 17 00:00:00 2001
From: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Date: Thu, 4 Apr 2019 17:44:46 +0300
Subject: [PATCH] arm64: dts: lx2160a: add interrupt property for aquantia phy
Add interrupt property for Aquantia AQR107 ethernet phy, currently
working in polling mode.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -184,14 +184,14 @@
aquantia_phy1: ethernet-phy@4 {
/* AQR107 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x4>;
- /* Poll mode - no "interrupts" property defined */
};
aquantia_phy2: ethernet-phy@5 {
/* AQR107 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5>;
- /* Poll mode - no "interrupts" property defined */
};
};

292
target/linux/layerscape/patches-5.4/302-dts-0051-arm64-dts-fsl-layerscape-fix-warnings-when-compiling.patch Normal file
View File

@ -0,0 +1,292 @@
From d949248dccef18f7257d8de0adfd67244955e7b7 Mon Sep 17 00:00:00 2001
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Mon, 22 Apr 2019 16:22:49 +0530
Subject: [PATCH] arm64: dts: fsl: layerscape: fix warnings when compiling dts
files
when compiling dts file using DTC_FLAG='-@', the device tree compiler
reports these warnings:
Warning (simple_bus_reg): /soc/mdio@0x8c0b000: simple-bus unit address
format error, expected "8c0b000"
Warning (unit_address_format): /pfe@04000000: unit name should not have
leading 0s
Fixed the node names to silence these warnings.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 14 +++++++-------
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 22 +++++++++++-----------
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 18 +++++++++---------
4 files changed, 29 insertions(+), 28 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1012A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*
*/
@@ -513,7 +514,7 @@
};
};
- pfe: pfe@04000000 {
+ pfe: pfe@4000000 {
compatible = "fsl,pfe";
reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
<0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@@ -310,7 +310,7 @@
};
/* TODO: WRIOP (CCSR?) */
- emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
+ emdio1: mdio@8B96000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO1: 0x1_6000
*/
compatible = "fsl,fman-memac-mdio";
@@ -323,7 +323,7 @@
#size-cells = <0>;
};
- emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
+ emdio2: mdio@8B97000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO2: 0x1_7000
*/
compatible = "fsl,fman-memac-mdio";
@@ -335,7 +335,7 @@
#size-cells = <0>;
};
- pcs_mdio1: mdio@0x8c07000 {
+ pcs_mdio1: mdio@8c07000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c07000 0x0 0x1000>;
device_type = "mdio";
@@ -345,7 +345,7 @@
#size-cells = <0>;
};
- pcs_mdio2: mdio@0x8c0b000 {
+ pcs_mdio2: mdio@8c0b000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0b000 0x0 0x1000>;
device_type = "mdio";
@@ -355,7 +355,7 @@
#size-cells = <0>;
};
- pcs_mdio3: mdio@0x8c0f000 {
+ pcs_mdio3: mdio@8c0f000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0f000 0x0 0x1000>;
device_type = "mdio";
@@ -365,7 +365,7 @@
#size-cells = <0>;
};
- pcs_mdio4: mdio@0x8c13000 {
+ pcs_mdio4: mdio@8c13000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c13000 0x0 0x1000>;
device_type = "mdio";
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
@@ -525,7 +525,7 @@
};
/* TODO: WRIOP (CCSR?) */
- emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
+ emdio1: mdio@8B96000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO1: 0x1_6000
*/
compatible = "fsl,fman-memac-mdio";
@@ -538,7 +538,7 @@
#size-cells = <0>;
};
- emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
+ emdio2: mdio@8B97000 { /* WRIOP0: 0x8B8_0000,
* E-MDIO2: 0x1_7000
*/
compatible = "fsl,fman-memac-mdio";
@@ -550,7 +550,7 @@
#size-cells = <0>;
};
- pcs_mdio1: mdio@0x8c07000 {
+ pcs_mdio1: mdio@8c07000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c07000 0x0 0x1000>;
device_type = "mdio";
@@ -560,7 +560,7 @@
#size-cells = <0>;
};
- pcs_mdio2: mdio@0x8c0b000 {
+ pcs_mdio2: mdio@8c0b000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0b000 0x0 0x1000>;
device_type = "mdio";
@@ -570,7 +570,7 @@
#size-cells = <0>;
};
- pcs_mdio3: mdio@0x8c0f000 {
+ pcs_mdio3: mdio@8c0f000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0f000 0x0 0x1000>;
device_type = "mdio";
@@ -580,7 +580,7 @@
#size-cells = <0>;
};
- pcs_mdio4: mdio@0x8c13000 {
+ pcs_mdio4: mdio@8c13000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c13000 0x0 0x1000>;
device_type = "mdio";
@@ -590,7 +590,7 @@
#size-cells = <0>;
};
- pcs_mdio5: mdio@0x8c17000 {
+ pcs_mdio5: mdio@8c17000 {
status = "disabled";
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c17000 0x0 0x1000>;
@@ -601,7 +601,7 @@
#size-cells = <0>;
};
- pcs_mdio6: mdio@0x8c1b000 {
+ pcs_mdio6: mdio@8c1b000 {
status = "disabled";
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c1b000 0x0 0x1000>;
@@ -612,7 +612,7 @@
#size-cells = <0>;
};
- pcs_mdio7: mdio@0x8c1f000 {
+ pcs_mdio7: mdio@8c1f000 {
status = "disabled";
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c1f000 0x0 0x1000>;
@@ -623,7 +623,7 @@
#size-cells = <0>;
};
- pcs_mdio8: mdio@0x8c23000 {
+ pcs_mdio8: mdio@8c23000 {
status = "disabled";
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c23000 0x0 0x1000>;
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
//
// Device Tree Include file for Layerscape-LX2160A family SoC.
//
-// Copyright 2018 NXP
+// Copyright 2018-2019 NXP
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -500,7 +500,7 @@
status = "disabled";
};
- pcs_mdio1: mdio@0x8c07000 {
+ pcs_mdio1: mdio@8c07000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c07000 0x0 0x1000>;
device_type = "mdio";
@@ -510,7 +510,7 @@
#size-cells = <0>;
};
- pcs_mdio2: mdio@0x8c0b000 {
+ pcs_mdio2: mdio@8c0b000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0b000 0x0 0x1000>;
device_type = "mdio";
@@ -520,7 +520,7 @@
#size-cells = <0>;
};
- pcs_mdio3: mdio@0x8c0f000 {
+ pcs_mdio3: mdio@8c0f000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0f000 0x0 0x1000>;
device_type = "mdio";
@@ -530,7 +530,7 @@
#size-cells = <0>;
};
- pcs_mdio4: mdio@0x8c13000 {
+ pcs_mdio4: mdio@8c13000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c13000 0x0 0x1000>;
device_type = "mdio";
@@ -540,7 +540,7 @@
#size-cells = <0>;
};
- pcs_mdio5: mdio@0x8c17000 {
+ pcs_mdio5: mdio@8c17000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c17000 0x0 0x1000>;
device_type = "mdio";
@@ -550,7 +550,7 @@
#size-cells = <0>;
};
- pcs_mdio6: mdio@0x8c1b000 {
+ pcs_mdio6: mdio@8c1b000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c1b000 0x0 0x1000>;
device_type = "mdio";
@@ -560,7 +560,7 @@
#size-cells = <0>;
};
- pcs_mdio7: mdio@0x8c1f000 {
+ pcs_mdio7: mdio@8c1f000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c1f000 0x0 0x1000>;
device_type = "mdio";
@@ -570,7 +570,7 @@
#size-cells = <0>;
};
- pcs_mdio8: mdio@0x8c23000 {
+ pcs_mdio8: mdio@8c23000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c23000 0x0 0x1000>;
device_type = "mdio";

114
target/linux/layerscape/patches-5.4/302-dts-0052-arm64-dts-fsl-layerscape-fix-warnings-when-compiling.patch Normal file
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@ -0,0 +1,114 @@
From 92aff696c8708ff5293eb000e98456e23afe1cb3 Mon Sep 17 00:00:00 2001
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Mon, 22 Apr 2019 16:43:13 +0530
Subject: [PATCH] arm64: dts: fsl: layerscape: fix warnings when compiling dts
files
when compiling dts file using DTC_FLAG='-@', the device tree compiler
reports these warnings:
Warning (alias_paths): /aliases: aliases property name must include
only lowercase and '-'
Fixed the node aliases to silence these warnings.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 34 +++++++++++------------
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 28 +++++++++----------
2 files changed, 31 insertions(+), 31 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*/
@@ -24,22 +24,22 @@
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
- sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
- sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
- sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
- sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
- qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
- qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
- qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
- qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
- qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
- qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
- qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
- qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
- emi1_slot1 = &ls1043mdio_s1;
- emi1_slot2 = &ls1043mdio_s2;
- emi1_slot3 = &ls1043mdio_s3;
- emi1_slot4 = &ls1043mdio_s4;
+ sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
+ sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
+ sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
+ sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
+ qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
+ qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
+ qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
+ qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
+ emi1-slot1 = &ls1043mdio_s1;
+ emi1-slot2 = &ls1043mdio_s2;
+ emi1-slot3 = &ls1043mdio_s3;
+ emi1-slot4 = &ls1043mdio_s4;
};
chosen {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*/
@@ -26,19 +26,19 @@
serial2 = &duart2;
serial3 = &duart3;
- emi1_slot1 = &ls1046mdio_s1;
- emi1_slot2 = &ls1046mdio_s2;
- emi1_slot4 = &ls1046mdio_s4;
-
- sgmii_s1_p1 = &sgmii_phy_s1_p1;
- sgmii_s1_p2 = &sgmii_phy_s1_p2;
- sgmii_s1_p3 = &sgmii_phy_s1_p3;
- sgmii_s1_p4 = &sgmii_phy_s1_p4;
- sgmii_s4_p1 = &sgmii_phy_s4_p1;
- qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
- qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
- qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
- qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
+ emi1-slot1 = &ls1046mdio_s1;
+ emi1-slot2 = &ls1046mdio_s2;
+ emi1-slot4 = &ls1046mdio_s4;
+
+ sgmii-s1-p1 = &sgmii_phy_s1_p1;
+ sgmii-s1-p2 = &sgmii_phy_s1_p2;
+ sgmii-s1-p3 = &sgmii_phy_s1_p3;
+ sgmii-s1-p4 = &sgmii_phy_s1_p4;
+ sgmii-s4-p1 = &sgmii_phy_s4_p1;
+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
};
chosen {

187
target/linux/layerscape/patches-5.4/302-dts-0053-sdk-arm64-dts-nxp-add-DPAA1-SDK-flavor-dts-files.patch Normal file
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@ -0,0 +1,187 @@
From 13fdde4dfdccd567ae459db6e439a53496732748 Mon Sep 17 00:00:00 2001
From: Pramod Kumar <pramod.kumar_1@nxp.com>
Date: Wed, 8 May 2019 18:25:16 +0530
Subject: [PATCH] sdk: arm64: dts: nxp: add DPAA1 SDK flavor dts files
dts fsl-ls1046a-frwy-sdk.dts which enables sdk specific entries
dts fsl-ls1046a-frwy-usdpaa.dts which enables dpdk
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts | 53 ++++++++++++
.../boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts | 99 ++++++++++++++++++++++
3 files changed, 154 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -13,6 +13,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-sdk.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy-usdpaa.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2019 NXP.
+ *
+ */
+
+#include "fsl-ls1046a-frwy.dts"
+#include "qoriq-qman-portals-sdk.dtsi"
+#include "qoriq-bman-portals-sdk.dtsi"
+
+&bman_fbpr {
+ compatible = "fsl,bman-fbpr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+&qman_pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&soc {
+#include "qoriq-dpaa-eth.dtsi"
+#include "qoriq-fman3-0-6oh.dtsi"
+};
+
+&fsldpaa {
+ ethernet@1 {
+ status = "disabled";
+ };
+ ethernet@2 {
+ status = "disabled";
+ };
+ ethernet@3 {
+ status = "disabled";
+ };
+ ethernet@6 {
+ status = "disabled";
+ };
+ ethernet@9 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet7>;
+ dma-coherent;
+ };
+};
+
+&fman0 {
+ compatible = "fsl,fman", "simple-bus";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2019 NXP.
+ *
+ */
+
+#include "fsl-ls1046a-frwy-sdk.dts"
+
+&soc {
+ bp7: buffer-pool@7 {
+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
+ fsl,bpid = <7>;
+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
+ };
+
+ bp8: buffer-pool@8 {
+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
+ fsl,bpid = <8>;
+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ };
+
+ bp9: buffer-pool@9 {
+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
+ fsl,bpid = <9>;
+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ };
+
+ fsl,dpaa {
+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
+
+ ethernet@0 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
+ fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
+ };
+
+ ethernet@4 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
+ fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
+ };
+
+ ethernet@5 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
+ };
+
+ ethernet@9 {
+ compatible = "fsl,dpa-ethernet-init";
+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
+ };
+
+ dpa-fman0-oh@2 {
+ compatible = "fsl,dpa-oh";
+ /* Define frame queues for the OH port*/
+ /* <OH Rx error, OH Rx default> */
+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
+ fsl,fman-oh-port = <&fman0_oh2>;
+ };
+ };
+};
+/ {
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ /* For legacy usdpaa based use-cases, update the size and
+ alignment parameters. e.g. to allocate 256 MB memory:
+ size = <0 0x10000000>;
+ alignment = <0 0x10000000>;
+ */
+
+ usdpaa_mem: usdpaa_mem {
+ compatible = "fsl,usdpaa-mem";
+ alloc-ranges = <0 0 0x10000 0>;
+ size = <0 0x1000>;
+ alignment = <0 0x1000>;
+ };
+ };
+};
+
+&fman0 {
+ fman0_oh2: port@83000 {
+ cell-index = <1>;
+ compatible = "fsl,fman-port-oh";
+ reg = <0x83000 0x1000>;
+ };
+};

40
target/linux/layerscape/patches-5.4/302-dts-0054-arm64-dts-nxp-frwy-ls1046a-add-support-for-micron-no.patch Normal file
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@ -0,0 +1,40 @@
From 3c013ab682fe1e6ca0473141f03f26e2f47980ad Mon Sep 17 00:00:00 2001
From: Pramod Kumar <pramod.kumar_1@nxp.com>
Date: Fri, 10 May 2019 14:33:37 +0530
Subject: [PATCH] arm64: dts: nxp: frwy-ls1046a: add support for micron nor
flash
add micron nor flash support for ls1046a frwy board.
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
@@ -112,6 +112,23 @@
};
+
+&qspi {
+ num-cs = <1>;
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
#include "fsl-ls1046-post.dtsi"
&fman0 {

71
target/linux/layerscape/patches-5.4/302-dts-0055-arm64-dts-ls1028a-Add-PCIe-controller-DT-nodes.patch Normal file
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@ -0,0 +1,71 @@
From 25291f86f449c4488a0a46b1e6b3ce3b83dbf1f9 Mon Sep 17 00:00:00 2001
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Date: Wed, 15 May 2019 10:14:30 +0800
Subject: [PATCH] arm64: dts: ls1028a: Add PCIe controller DT nodes
LS1028a implements 2 PCIe 3.0 controllers.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 50 ++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -631,6 +631,56 @@
};
};
+ pcie@3400000 {
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
pcie@1f0000000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf0000000 0x0 0x100000>;

34
target/linux/layerscape/patches-5.4/302-dts-0056-arm64-dts-lx2160a-Enable-usb3-lpm-capable-for-usb3-n.patch Normal file
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@ -0,0 +1,34 @@
From 74f9f7ee3f4b2e88bd29e7ac3dbc6a8ffe2e97f9 Mon Sep 17 00:00:00 2001
From: Ran Wang <ran.wang_1@nxp.com>
Date: Wed, 15 May 2019 13:33:49 +0800
Subject: [PATCH] arm64: dts: lx2160a: Enable usb3-lpm-capable for usb3 node
Enable USB3 HW LPM feature for lx2160a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -843,6 +843,8 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
@@ -855,6 +857,8 @@
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ usb3-lpm-capable;
+ snps,dis-u1u2-when-u3-quirk;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;

103
target/linux/layerscape/patches-5.4/302-dts-0057-arm64-dts-fsl-lx2160a-add-flexcan-node.patch Normal file
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@ -0,0 +1,103 @@
From c2046901f933b0e1c87c5cbdab4ba27a3b66317e Mon Sep 17 00:00:00 2001
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Wed, 8 May 2019 17:49:14 +0530
Subject: [PATCH] arm64: dts: fsl: lx2160a: add flexcan node
Add flexcan node in LX2160A SOC file as well as in QDS and RDB files.
The device tree bindings used can be referred from
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 10 +++++++++-
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 18 +++++++++++++++++-
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 18 ++++++++++++++++++
3 files changed, 44 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -2,7 +2,7 @@
//
// Device Tree file for LX2160AQDS
//
-// Copyright 2018 NXP
+// Copyright 2018-2019 NXP
/dts-v1/;
@@ -155,6 +155,14 @@
};
};
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
&crypto {
status = "okay";
};
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -2,7 +2,7 @@
//
// Device Tree file for LX2160ARDB
//
-// Copyright 2018 NXP
+// Copyright 2018-2019 NXP
/dts-v1/;
@@ -31,6 +31,22 @@
};
};
+&can0 {
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
&crypto {
status = "okay";
};
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -753,6 +753,24 @@
status = "disabled";
};
+ can0: can@2180000 {
+ compatible = "fsl,lx2160ar1-flexcan";
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>, <&clockgen 4 7>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can1: can@2190000 {
+ compatible = "fsl,lx2160ar1-flexcan";
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>, <&clockgen 4 7>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
uart0: serial@21c0000 {
compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21c0000 0x0 0x1000>;

114
target/linux/layerscape/patches-5.4/302-dts-0058-arm64-dts-fsl-ls1028a-add-flexcan-node.patch Normal file
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@ -0,0 +1,114 @@
From 3724107421d95c5a46b19b950b04de2a05c1f757 Mon Sep 17 00:00:00 2001
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Wed, 8 May 2019 17:49:14 +0530
Subject: [PATCH] arm64: dts: fsl: ls1028a: add flexcan node
Add flexcan node in LS1028A SOC file as well as in QDS and RDB files.
The device tree bindings used can be referred from
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 10 +++++++++-
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 18 +++++++++++++++++-
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 22 +++++++++++++++++++++-
3 files changed, 47 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1028A QDS Board.
*
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@@ -107,6 +107,14 @@
};
};
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
&duart0 {
status = "okay";
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -2,7 +2,7 @@
/*
* Device Tree file for NXP LS1028A RDB Board.
*
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@@ -152,6 +152,22 @@
};
};
+&can0 {
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
&duart0 {
status = "okay";
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1028A family SoC.
*
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
@@ -287,6 +287,26 @@
status = "disabled";
};
+ can0: can@2180000 {
+ compatible = "fsl,ls1028ar1-flexcan",
+ "fsl,lx2160ar1-flexcan";
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>, <&clockgen 4 1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can1: can@2190000 {
+ compatible = "fsl,ls1028ar1-flexcan",
+ "fsl,lx2160ar1-flexcan";
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>, <&clockgen 4 1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;

55
target/linux/layerscape/patches-5.4/302-dts-0059-arm64-dts-fsl-ls1046-Modify-the-qspi-flash-frequency.patch Normal file
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@ -0,0 +1,55 @@
From 0a4e4723a1765770bb04ec4a5ad427b2c97627b6 Mon Sep 17 00:00:00 2001
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Tue, 21 May 2019 20:26:29 +0530
Subject: [PATCH] arm64: dts: fsl: ls1046: Modify the qspi flash frequency
The qspi flash in ls1046a based QDS and RDB boards can operate
at 50MHz frequency.
Therefore, update the maximum supported freq in their respective
dts files.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -184,7 +184,7 @@
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <0>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@@ -106,7 +107,7 @@
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <0>;
@@ -116,7 +117,7 @@
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <1>;

87
target/linux/layerscape/patches-5.4/302-dts-0060-arm64-dts-ls1028a-add-flexspi-nodes.patch Normal file
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@ -0,0 +1,87 @@
From b94cbaaa2facfdc6aa49d6f323da251f9e91d4ba Mon Sep 17 00:00:00 2001
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Date: Tue, 14 May 2019 18:17:31 +0800
Subject: [PATCH] arm64: dts: ls1028a: add flexspi nodes
Add fspi node property for LS1028A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LS1028ARDB and LS1028AQDS target.
This is having one SPI-NOR flash device, mt35xu02g connected at
CS0.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 15 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 15 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 12 ++++++++++++
3 files changed, 42 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -222,6 +222,21 @@
phy-connection-type = "rgmii-id";
};
+&fspi {
+ status = "okay";
+ mt35xu02g: flash@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
+ spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+ };
+};
+
&sai1 {
status = "okay";
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -168,6 +168,21 @@
};
};
+&fspi {
+ status = "okay";
+ mt35xu02g: flash@0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
+ spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+ };
+};
+
&duart0 {
status = "okay";
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -180,6 +180,18 @@
clocks = <&sysclk>;
};
+ fspi: spi@20c0000 {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "FSPI", "FSPI-memory";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "fspi_en", "fspi";
+ };
+
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;

61
target/linux/layerscape/patches-5.4/302-dts-0061-sdk-dts-ls1046-drop-smmu-from-the-frwy-sdk-dtses.patch Normal file
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@ -0,0 +1,61 @@
From 68148cb462754f0f79b77aa56ea0e8ec899ead36 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Tue, 28 May 2019 13:35:56 +0300
Subject: [PATCH] sdk: dts: ls1046: drop smmu from the frwy sdk dtses
Drop the smmu from the frwy and frwy-usdpaa versions of the SDK device
trees because SMMU is supported only for the upstream version of the
dpaa ethernet drivers.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts | 14 ++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts | 14 ++++++++++++++
2 files changed, 28 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts
@@ -26,6 +26,20 @@
&soc {
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
+
+ pcie@3400000 {
+ /delete-property/ iommu-map;
+ };
+
+ pcie@3500000 {
+ /delete-property/ iommu-map;
+ };
+
+ pcie@3600000 {
+ /delete-property/ iommu-map;
+ };
+
+ /delete-node/ iommu@9000000;
};
&fsldpaa {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts
@@ -69,6 +69,20 @@
fsl,fman-oh-port = <&fman0_oh2>;
};
};
+
+ pcie@3400000 {
+ /delete-property/ iommu-map;
+ };
+
+ pcie@3500000 {
+ /delete-property/ iommu-map;
+ };
+
+ pcie@3600000 {
+ /delete-property/ iommu-map;
+ };
+
+ /delete-node/ iommu@9000000;
};
/ {
reserved-memory {

235
target/linux/layerscape/patches-5.4/302-dts-0062-sdk-dts-ls1046frwy-move-dma-coherent-from-soc-to-its.patch Normal file
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@ -0,0 +1,235 @@
From 7d5fcedd45e066db0d2735a753a86af31ba44722 Mon Sep 17 00:00:00 2001
From: Ran Wang <ran.wang_1@nxp.com>
Date: Wed, 29 May 2019 16:18:06 +0800
Subject: [PATCH] sdk: dts: ls1046frwy move dma-coherent from soc to its child
nodes
Since SMMU is not supported for SDK version, USB function will down if
still apply property 'dma-coherent' in scope of soc (USB driver is not
ready to support it alone) in SDK device trees, decide to remove it.
And add dma-coherent on other non-USB child nodes under soc.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
.../boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts | 174 +++++++++++++++++++++
.../boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts | 4 +
2 files changed, 178 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts
@@ -24,6 +24,8 @@
};
&soc {
+/delete-property/ dma-coherent;
+
#include "qoriq-dpaa-eth.dtsi"
#include "qoriq-fman3-0-6oh.dtsi"
@@ -65,3 +67,175 @@
&fman0 {
compatible = "fsl,fman", "simple-bus";
};
+
+&clockgen {
+ dma-coherent;
+};
+
+&scfg {
+ dma-coherent;
+};
+
+&crypto {
+ dma-coherent;
+};
+
+&dcfg {
+ dma-coherent;
+};
+
+&ifc {
+ dma-coherent;
+};
+
+&qspi {
+ dma-coherent;
+};
+
+&esdhc {
+ dma-coherent;
+};
+
+&ddr {
+ dma-coherent;
+};
+
+&tmu {
+ dma-coherent;
+};
+
+&qman {
+ dma-coherent;
+};
+
+&bman {
+ dma-coherent;
+};
+
+&bportals {
+ dma-coherent;
+};
+
+&qportals {
+ dma-coherent;
+};
+
+&dspi {
+ dma-coherent;
+};
+
+&i2c0 {
+ dma-coherent;
+};
+
+&i2c1 {
+ dma-coherent;
+};
+
+&i2c2 {
+ dma-coherent;
+};
+
+&i2c3 {
+ dma-coherent;
+};
+
+&duart0 {
+ dma-coherent;
+};
+
+&duart1 {
+ dma-coherent;
+};
+
+&duart2 {
+ dma-coherent;
+};
+
+&duart3 {
+ dma-coherent;
+};
+
+&gpio0 {
+ dma-coherent;
+};
+
+&gpio1 {
+ dma-coherent;
+};
+
+&gpio2 {
+ dma-coherent;
+};
+
+&gpio3 {
+ dma-coherent;
+};
+
+&lpuart0 {
+ dma-coherent;
+};
+
+&lpuart1 {
+ dma-coherent;
+};
+
+&lpuart2 {
+ dma-coherent;
+};
+
+&lpuart3 {
+ dma-coherent;
+};
+
+&lpuart4 {
+ dma-coherent;
+};
+
+&lpuart5 {
+ dma-coherent;
+};
+
+&ftm0 {
+ dma-coherent;
+};
+
+&wdog0 {
+ dma-coherent;
+};
+
+&edma0 {
+ dma-coherent;
+};
+
+&sata {
+ dma-coherent;
+};
+
+&qdma {
+ dma-coherent;
+};
+
+&msi1 {
+ dma-coherent;
+};
+
+&msi2 {
+ dma-coherent;
+};
+
+&msi3 {
+ dma-coherent;
+};
+
+&fman0 {
+ dma-coherent;
+};
+
+&ptp_timer0 {
+ dma-coherent;
+};
+
+&fsldpaa {
+ dma-coherent;
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-usdpaa.dts
@@ -14,6 +14,7 @@
fsl,bpid = <7>;
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
+ dma-coherent;
};
bp8: buffer-pool@8 {
@@ -21,6 +22,7 @@
fsl,bpid = <8>;
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ dma-coherent;
};
bp9: buffer-pool@9 {
@@ -28,10 +30,12 @@
fsl,bpid = <9>;
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
+ dma-coherent;
};
fsl,dpaa {
compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
+ dma-coherent;
ethernet@0 {
compatible = "fsl,dpa-ethernet-init";

574
target/linux/layerscape/patches-5.4/302-dts-0063-arm64-dts-fsl-remove-backplane-support.patch Normal file
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@ -0,0 +1,574 @@
From 278bacf54eabe391159cef3112f8e8bf0fa7b891 Mon Sep 17 00:00:00 2001
From: Florinel Iordache <florinel.iordache@nxp.com>
Date: Mon, 27 May 2019 15:57:05 +0300
Subject: [PATCH] arm64: dts: fsl: remove backplane support
Remove entire backplane support from device tree for all supported platforms
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
---
.../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 4 -
.../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 34 --------
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 --
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 26 -------
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 46 -----------
arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 58 --------------
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 90 ----------------------
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 60 ---------------
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 86 ---------------------
.../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 4 +-
.../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 4 +-
11 files changed, 4 insertions(+), 413 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
@@ -259,10 +259,6 @@ pcie@3600000 {
dma-coherent;
};
-&serdes1 {
- dma-coherent;
-};
-
&fsldpaa {
dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
@@ -100,36 +100,6 @@ pcie@3600000 {
compatible = "fsl,fman", "simple-bus";
};
-&mdio9 {
- pcsphy6: ethernet-phy@0 {
- backplane-mode = "10gbase-kr";
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0x8C0 0x40>; /* lane D */
- };
-};
-
-&mdio10 {
- pcsphy7: ethernet-phy@0 {
- backplane-mode = "10gbase-kr";
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0x880 0x40>; /* lane C */
- };
-};
-
-/* Update MAC connections to backplane PHYs
- * &mac9 {
- * phy-handle = <&pcsphy6>;
- *};
- *
- *&mac10 {
- * phy-handle = <&pcsphy7>;
- *};
-*/
-
&clockgen {
dma-coherent;
};
@@ -298,10 +268,6 @@ pcie@3600000 {
dma-coherent;
};
-&serdes1 {
- dma-coherent;
-};
-
&fsldpaa {
dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -679,11 +679,6 @@
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
};
- serdes1: serdes@1ea0000 {
- reg = <0x0 0x1ea0000 0 0x00002000>;
- compatible = "fsl,serdes-10g";
- };
-
pcie@3400000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
@@ -170,29 +170,3 @@
&sata {
status = "okay";
};
-
-&pcs_mdio1 {
- pcs_phy1: ethernet-phy@0 {
- backplane-mode = "10gbase-kr";
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0x840 0x40>;/* lane B */
- };
-};
-
-&pcs_mdio2 {
- pcs_phy2: ethernet-phy@0 {
- backplane-mode = "10gbase-kr";
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0x800 0x40>;/* lane A */
- };
-};
-
-/* Update DPMAC connections to backplane PHYs, under SerDes 0x1D_0xXX.
- * &dpmac1 {
- * phy-handle = <&pcs_phy1>;
- * };
- */
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -183,12 +183,6 @@
little-endian;
};
- serdes1: serdes@1ea0000 {
- compatible = "fsl,serdes-10g";
- reg = <0x0 0x1ea0000 0 0x00002000>;
- little-endian;
- };
-
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
@@ -333,46 +327,6 @@
#address-cells = <1>;
#size-cells = <0>;
- };
-
- pcs_mdio1: mdio@8c07000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c07000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio2: mdio@8c0b000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c0b000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio3: mdio@8c0f000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c0f000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio4: mdio@8c13000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c13000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
};
ifc: ifc@2240000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
@@ -71,64 +71,6 @@
};
};
-&pcs_mdio1 {
- pcs_phy1: ethernet-phy@0 {
- backplane-mode = "10gbase-kr";
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0x9C0 0x40>;/* lane H */
- };
-};
-
-&pcs_mdio2 {
- pcs_phy2: ethernet-phy@0 {
- backplane-mode = "10gbase-kr";
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0x980 0x40>;/* lane G */
- };
-};
-
-&pcs_mdio3 {
- pcs_phy3: ethernet-phy@0 {
- backplane-mode = "10gbase-kr";
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0x940 0x40>;/* lane F */
- };
-};
-
-&pcs_mdio4 {
- pcs_phy4: ethernet-phy@0 {
- backplane-mode = "10gbase-kr";
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0x900 0x40>;/* lane E */
- };
-};
-
-/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
- * &dpmac1 {
- * phy-handle = <&pcs_phy1>;
- * };
- *
- * &dpmac2 {
- * phy-handle = <&pcs_phy2>;
- * };
- *
- * &dpmac3 {
- * phy-handle = <&pcs_phy3>;
- * };
- *
- * &dpmac4 {
- * phy-handle = <&pcs_phy4>;
- * };
- */
-
/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
&dpmac9 {
phy-handle = <&mdio0_phy12>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -550,90 +550,6 @@
#size-cells = <0>;
};
- pcs_mdio1: mdio@8c07000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c07000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio2: mdio@8c0b000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c0b000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio3: mdio@8c0f000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c0f000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio4: mdio@8c13000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c13000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio5: mdio@8c17000 {
- status = "disabled";
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c17000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio6: mdio@8c1b000 {
- status = "disabled";
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c1b000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio7: mdio@8c1f000 {
- status = "disabled";
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c1f000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio8: mdio@8c23000 {
- status = "disabled";
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c23000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
i2c0: i2c@2000000 {
status = "disabled";
compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
@@ -835,12 +751,6 @@
snps,host-vbus-glitches;
};
- serdes1: serdes@1ea0000 {
- compatible = "fsl,serdes-10g";
- reg = <0x0 0x1ea0000 0 0x00002000>;
- little-endian;
- };
-
ccn@4000000 {
compatible = "arm,ccn-504";
reg = <0x0 0x04000000 0x0 0x01000000>;
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -316,46 +316,6 @@
status = "okay";
};
-&pcs_mdio1 {
- pcs_phy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- backplane-mode = "40gbase-kr";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */
- };
-};
-
-&pcs_mdio2 {
- pcs_phy2: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- backplane-mode = "40gbase-kr";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */
- };
-};
-
-&pcs_mdio3 {
- pcs_phy3: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- backplane-mode = "10gbase-kr";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0xF00 0x100>; /* lane H */
- };
-};
-
-&pcs_mdio4 {
- pcs_phy4: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- backplane-mode = "10gbase-kr";
- reg = <0x0>;
- fsl,lane-handle = <&serdes1>;
- fsl,lane-reg = <0xE00 0x100>; /* lane G */
- };
-};
-
&sata0 {
status = "okay";
};
@@ -371,23 +331,3 @@
&sata3 {
status = "okay";
};
-
-/* Update DPMAC connections to 40G backplane PHYs
- * &dpmac1 {
- * phy-handle = <&pcs_phy1>;
- * };
- *
- * &dpmac2 {
- * phy-handle = <&pcs_phy2>;
- * };
- */
-
-/* Update DPMAC connections to 10G backplane PHYs
- * &dpmac3 {
- * phy-handle = <&pcs_phy3>;
- * };
- *
- * &dpmac4 {
- * phy-handle = <&pcs_phy4>;
- * };
- */
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -500,92 +500,6 @@
status = "disabled";
};
- pcs_mdio1: mdio@8c07000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c07000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio2: mdio@8c0b000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c0b000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio3: mdio@8c0f000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c0f000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio4: mdio@8c13000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c13000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio5: mdio@8c17000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c17000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio6: mdio@8c1b000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c1b000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio7: mdio@8c1f000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c1f000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- pcs_mdio8: mdio@8c23000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0x0 0x8c23000 0x0 0x1000>;
- device_type = "mdio";
- little-endian;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- serdes1: serdes@1ea0000 {
- compatible = "fsl,serdes-28g";
- reg = <0x0 0x1ea0000 0 0x00002000>;
- little-endian;
- };
-
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
@@ -22,7 +22,7 @@ fman@1a00000 {
fsl,qman-channel-id = <0x800>;
};
- mac9: ethernet@f0000 {
+ ethernet@f0000 {
cell-index = <0x8>;
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
@@ -30,7 +30,7 @@ fman@1a00000 {
pcsphy-handle = <&pcsphy6>;
};
- mdio9: mdio@f1000 {
+ mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
@@ -22,7 +22,7 @@ fman@1a00000 {
fsl,qman-channel-id = <0x801>;
};
- mac10: ethernet@f2000 {
+ ethernet@f2000 {
cell-index = <0x9>;
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
@@ -30,7 +30,7 @@ fman@1a00000 {
pcsphy-handle = <&pcsphy7>;
};
- mdio10: mdio@f3000 {
+ mdio@f3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";

31
target/linux/layerscape/patches-5.4/302-dts-0064-arm64-dts-lx2160a-update-interrupt-property-for-Aqua.patch Normal file
View File

@ -0,0 +1,31 @@
From e463f4a9d933d2d62a065bba356a9eb04a9f3ac0 Mon Sep 17 00:00:00 2001
From: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Date: Tue, 11 Jun 2019 23:53:45 +0300
Subject: [PATCH] arm64: dts: lx2160a: update interrupt property for Aquantia
phy
Update Aquantia AQR107 nodes interrupt property.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -200,13 +200,13 @@
aquantia_phy1: ethernet-phy@4 {
/* AQR107 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-ieee802.3-c45";
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x4>;
};
aquantia_phy2: ethernet-phy@5 {
/* AQR107 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-ieee802.3-c45";
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5>;
};
};

21
target/linux/layerscape/patches-5.4/302-dts-0065-arm64-dts-ls1028a-Update-fspi-reg-properties.patch Normal file
View File

@ -0,0 +1,21 @@
From bfd089c26a8b3c1eb83c94dc0f72c0f80fb7e5ef Mon Sep 17 00:00:00 2001
From: Kuldeep Singh <kuldeep.singh@nxp.com>
Date: Fri, 14 Jun 2019 12:34:14 +0530
Subject: [PATCH] arm64: dts: ls1028a: Update fspi reg properties
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -186,7 +186,7 @@
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
- reg-names = "FSPI", "FSPI-memory";
+ reg-names = "fspi_base", "fspi_mmap";
interrupts = <0 25 0x4>; /* Level high type */
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "fspi_en", "fspi";

31
target/linux/layerscape/patches-5.4/302-dts-0066-arm64-dts-ls1028a-add-gpu-node.patch Normal file
View File

@ -0,0 +1,31 @@
From 3e04a861ff536927ede8e826b7c4a5bf6a80dda7 Mon Sep 17 00:00:00 2001
From: Yuantian Tang <andy.tang@nxp.com>
Date: Tue, 18 Jun 2019 01:29:49 -0400
Subject: [PATCH] arm64: dts: ls1028a: add gpu node
Add GPU dts node to enable GPU feature.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -538,6 +538,16 @@
clock-names = "apb_pclk", "wdog_clk";
};
+ gpu@f0c0000 {
+ compatible = "fsl,ls1028a-gpu";
+ reg = <0x0 0x0f0c0000 0x0 0x10000>,
+ <0x0 0x80000000 0x0 0x80000000>,
+ <0x0 0x0 0x0 0x3000000>;
+ reg-names = "base", "phys_baseaddr",
+ "contiguous_mem";
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
sai1: audio-controller@f100000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";

29
target/linux/layerscape/patches-5.4/302-dts-0067-arm64-dts-fsl-add-optee-node-for-ls1028.patch Normal file
View File

@ -0,0 +1,29 @@
From 1021f327657a464fbe8bd9eab927f18b8cf7556e Mon Sep 17 00:00:00 2001
From: Sahil Malhotra <sahil.malhotra@nxp.com>
Date: Sat, 3 Aug 2019 09:45:28 +0530
Subject: [PATCH] arm64: dts: fsl: add optee node for ls1028
For enabling OP-TEE on LS1028, need to add optee node
in DTS
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -771,6 +771,13 @@
};
};
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
malidp0: display@f080000 {
compatible = "arm,mali-dp500";
reg = <0x0 0xf080000 0x0 0x10000>;

30
target/linux/layerscape/patches-5.4/302-dts-0068-arm64-dts-lx2160a-Update-phy-mode-for-Aquantia-PHYs.patch Normal file
View File

@ -0,0 +1,30 @@
From 6915b8ddc149601e6f0baf4836f0f9f18e3ee25f Mon Sep 17 00:00:00 2001
From: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Date: Wed, 24 Jul 2019 20:22:57 +0300
Subject: [PATCH] arm64: dts: lx2160a: Update phy mode for Aquantia PHYs
The Aquantia driver does not allow xgmii mode anymore for
the AQR107 PHYs. Use the correct usxgmii mode instead.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -220,12 +220,12 @@
&dpmac3 {
phy-handle = <&aquantia_phy1>;
- phy-connection-type = "xgmii";
+ phy-connection-type = "usxgmii";
};
&dpmac4 {
phy-handle = <&aquantia_phy2>;
- phy-connection-type = "xgmii";
+ phy-connection-type = "usxgmii";
};
&dpmac5 {

46
target/linux/layerscape/patches-5.4/302-dts-0069-arm64-dts-ls1028a-Add-ftm_alarm0-DT-node.patch Normal file
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@ -0,0 +1,46 @@
From cc4f01aa78bfbebd7bdb52b4d873b5c9a332319e Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Thu, 27 Jun 2019 14:24:29 +0800
Subject: [PATCH] arm64: dts: ls1028a: Add ftm_alarm0 DT node
The patch adds ftm_alarm0 DT node for LS1028ARDB board
FlexTimer1 module is used to wakeup the system
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -17,6 +17,10 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ rtc1 = &ftm_alarm0;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -769,6 +773,19 @@
little-endian;
};
};
+
+ rcpm: rcpm@1e34040 {
+ compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x1c>;
+ #fsl,rcpm-wakeup-cells = <7>;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls1028a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
firmware {

297
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@ -0,0 +1,297 @@
From c97c6ebf6fd6a6ff72bd7d58a12de0c07f14953e Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Thu, 27 Jun 2019 15:02:44 +0800
Subject: [PATCH] arm64: dts: ls1012a/ls1043a/ls1046a/ls1088a/ls208xa: replace
ftm0 with ftm_alarm0
The patch replaces ftm0 with ftm_alarm0 DT node
- replace ftm0 with ftm_alarm0
- add new rcpm node
- remove old rcpm node
- aliases ftm_alarm0 as rtc1
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 23 +++++++++++----------
.../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 2 +-
.../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 24 +++++++++++++---------
.../boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts | 2 +-
.../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 2 +-
.../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 24 ++++++++++++++--------
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 20 ++++++++++++------
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 12 +++++++++--
10 files changed, 70 insertions(+), 43 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -23,6 +23,7 @@
rtic-c = &rtic_c;
rtic-d = &rtic_d;
sec-mon = &sec_mon;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -289,15 +290,21 @@
#thermal-sensor-cells = <1>;
};
- ftm0: ftm0@29d0000 {
- compatible = "fsl,ftm-alarm";
- reg = <0x0 0x29d0000 0x0 0x10000>,
- <0x0 0x1ee2140 0x0 0x4>;
- reg-names = "ftm", "FlexTimer1";
+ rcpm: rcpm@1ee2140 {
+ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1012a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
interrupts = <0 86 0x4>;
big-endian;
};
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
#address-cells = <1>;
@@ -496,12 +503,6 @@
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
-
- rcpm: rcpm@1ee2000 {
- compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
- reg = <0x0 0x1ee2000 0x0 0x1000>;
- fsl,#rcpm-wakeup-cells = <1>;
- };
};
reserved-memory {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
@@ -226,7 +226,7 @@ pcie@3600000 {
dma-coherent;
};
-&ftm0 {
+&ftm_alarm0 {
dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
@@ -221,7 +221,7 @@ pcie@3600000 {
dma-coherent;
};
-&ftm0 {
+&ftm_alarm0 {
dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -27,6 +27,7 @@
ethernet4 = &enet4;
ethernet5 = &enet5;
ethernet6 = &enet6;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -660,16 +661,6 @@
status = "disabled";
};
- ftm0: ftm0@29d0000 {
- compatible = "fsl,ftm-alarm";
- reg = <0x0 0x29d0000 0x0 0x10000>,
- <0x0 0x1ee2140 0x0 0x4>;
- reg-names = "ftm", "FlexTimer1";
- interrupts = <0 86 0x4>;
- big-endian;
- status = "okay";
- };
-
wdog0: wdog@2ad0000 {
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
@@ -874,6 +865,19 @@
big-endian;
};
+ rcpm: rcpm@1ee2140 {
+ compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1043a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
+ interrupts = <0 86 0x4>;
+ big-endian;
+ };
};
firmware {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy-sdk.dts
@@ -196,7 +196,7 @@
dma-coherent;
};
-&ftm0 {
+&ftm_alarm0 {
dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
@@ -223,7 +223,7 @@ pcie@3600000 {
dma-coherent;
};
-&ftm0 {
+&ftm_alarm0 {
dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
@@ -228,7 +228,7 @@ pcie@3600000 {
dma-coherent;
};
-&ftm0 {
+&ftm_alarm0 {
dma-coherent;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -28,6 +28,7 @@
ethernet5 = &enet5;
ethernet6 = &enet6;
ethernet7 = &enet7;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -560,15 +561,6 @@
status = "disabled";
};
- ftm0: ftm0@29d0000 {
- compatible = "fsl,ftm-alarm";
- reg = <0x0 0x29d0000 0x0 0x10000>,
- <0x0 0x1ee2140 0x0 0x4>;
- reg-names = "ftm", "FlexTimer1";
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
- };
-
wdog0: watchdog@2ad0000 {
compatible = "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
@@ -810,6 +802,20 @@
queue-sizes = <64 64>;
big-endian;
};
+
+ rcpm: rcpm@1ee208c {
+ compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee208c 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1046a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
};
reserved-memory {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -18,6 +18,7 @@
aliases {
crypto = &crypto;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -339,12 +340,6 @@
status = "disabled";
};
- ftm0: ftm0@2800000 {
- compatible = "fsl,ftm-alarm";
- reg = <0x0 0x2800000 0x0 0x10000>;
- interrupts = <0 44 4>;
- };
-
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c";
#address-cells = <1>;
@@ -792,6 +787,19 @@
};
};
};
+
+ rcpm: rcpm@1e34040 {
+ compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x18>;
+ #fsl,rcpm-wakeup-cells = <6>;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls1088a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
+ interrupts = <0 44 4>;
+ };
};
firmware {
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -24,6 +24,7 @@
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
+ rtc1 = &ftm_alarm0;
};
cpu: cpus {
@@ -757,9 +758,16 @@
interrupts = <0 12 4>;
};
- ftm0: ftm0@2800000 {
- compatible = "fsl,ftm-alarm";
+ rcpm: rcpm@1e34040 {
+ compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x18>;
+ #fsl,rcpm-wakeup-cells = <6>;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls208xa-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
interrupts = <0 44 4>;
};
};

62
target/linux/layerscape/patches-5.4/302-dts-0071-arm-dts-ls1021a-replace-ftm0-with-ftm_alarm0-DT-node.patch Normal file
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@ -0,0 +1,62 @@
From f3a115bd1372e774979ecb81919664279b81810e Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Fri, 28 Jun 2019 16:36:20 +0800
Subject: [PATCH] arm: dts: ls1021a: replace ftm0 with ftm_alarm0 DT node
The patch replaces ftm0 with ftm_alarm0 DT node
- remove old ftm0 node
- add rcpm node
- add ftm_alarm0 node
- aliases ftm_alarm0 as rtc1
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -66,6 +66,7 @@
serial4 = &lpuart4;
serial5 = &lpuart5;
sysclk = &sysclk;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -582,16 +583,6 @@
status = "disabled";
};
- ftm0: ftm0@29d0000 {
- compatible = "fsl,ftm-alarm";
- reg = <0x0 0x29d0000 0x0 0x10000>,
- <0x0 0x1ee2140 0x0 0x4>;
- reg-names = "ftm", "FlexTimer1";
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
- status = "okay";
- };
-
pwm1: pwm@29e0000 {
compatible = "fsl,vf610-ftm-pwm";
#pwm-cells = <3>;
@@ -1003,5 +994,18 @@
big-endian;
};
+ rcpm: rcpm@1ee2140 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x8>;
+ #fsl,rcpm-wakeup-cells = <2>;
+ };
+
+ ftm_alarm0: timer0@29d0000 {
+ compatible = "fsl,ls1021a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
};
};

31
target/linux/layerscape/patches-5.4/302-dts-0072-arm64-ls1028ardb-Add-support-DP-nodes-for-LS1028ARDB.patch Normal file
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@ -0,0 +1,31 @@
From b778a15d8781263bb768c404965dd5ec4bbe80c8 Mon Sep 17 00:00:00 2001
From: Wen He <wen.he_1@nxp.com>
Date: Wed, 17 Jul 2019 15:04:13 +0800
Subject: [PATCH] arm64: ls1028ardb: Add support DP nodes for LS1028ARDB
This patch add HDP PHY Controller related nodes on the LS1028ARDB.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -215,3 +215,15 @@
&sata {
status = "okay";
};
+
+&hdptx0 {
+ fsl,no_edid;
+ resolution = "3840x2160@60",
+ "1920x1080@60",
+ "1280x720@60",
+ "720x480@60";
+ lane_mapping = <0x4e>;
+ edp_link_rate = <0x6>;
+ edp_num_lanes = <0x4>;
+ status = "okay";
+};

31
target/linux/layerscape/patches-5.4/302-dts-0073-arm64-ls1028aqds-Add-support-DP-nodes-for-LS1028AQDS.patch Normal file
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@ -0,0 +1,31 @@
From 3e4421bc3d2055d599c65d5519b1eb63c0b9468e Mon Sep 17 00:00:00 2001
From: Wen He <wen.he_1@nxp.com>
Date: Wed, 17 Jul 2019 15:06:06 +0800
Subject: [PATCH] arm64: ls1028aqds: Add support DP nodes for LS1028AQDS
This patch add HDP PHY Controller related nodes on the LS1028AQDS.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -244,3 +244,15 @@
&sata {
status = "okay";
};
+
+&hdptx0 {
+ fsl,no_edid;
+ resolution = "3840x2160@60",
+ "1920x1080@60",
+ "1280x720@60",
+ "720x480@60";
+ lane_mapping = <0x4e>;
+ edp_link_rate = <0x6>;
+ edp_num_lanes = <0x4>;
+ status = "okay";
+};

102
target/linux/layerscape/patches-5.4/302-dts-0074-arm64-dts-fsl-ls1028a-Add-Felix-switch-port-DT-node.patch Normal file
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@ -0,0 +1,102 @@
From f5f011742b6ec9ad1db54de9e8296f1d5a3ede8a Mon Sep 17 00:00:00 2001
From: Claudiu Manoil <claudiu.manoil@nxp.com>
Date: Fri, 14 Jun 2019 19:24:27 +0300
Subject: [PATCH] arm64: dts: fsl: ls1028a: Add Felix switch port DT node
Add the switch device node, available on PF5, so that the
switch port sub-nodes (net devices) can be linked to
corresponding board specific phy nodes (external ports) or
have their link mode defined (internal ports).
The switch device features 6 ports, 4 with external links
and 2 internally facing to the ls1028a SoC and connected via
fixed links to 2 internal enetc ethernet contoller ports.
Add the corresponding enetc internal port device nodes,
mapped to PF2 and PF6 PCIe functions.
And don't forget to enable the 4MB BAR4 in the root complex
ECAM space, where the switch registers are mapped.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 58 +++++++++++++++++++++++++-
1 file changed, 57 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -750,7 +750,9 @@
/* PF1: VF0-1 BAR0 - non-prefetchable memory */
0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
/* PF1: VF0-1 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>;
+ 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
+ /* BAR4 (PF5) - non-prefetchable memory */
+ 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
enetc_port0: ethernet@0,0 {
compatible = "fsl,enetc";
@@ -766,12 +768,66 @@
#address-cells = <1>;
#size-cells = <0>;
};
+ ethernet@0,2 {
+ compatible = "fsl,enetc";
+ reg = <0x000200 0 0 0 0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
ethernet@0,4 {
compatible = "fsl,enetc-ptp";
reg = <0x000400 0 0 0 0>;
clocks = <&clockgen 4 0>;
little-endian;
};
+ switch@0,5 {
+ compatible = "mscc,felix-switch";
+ reg = <0x000500 0 0 0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* external ports */
+ switch_port0: port@0 {
+ reg = <0>;
+ };
+ switch_port1: port@1 {
+ reg = <1>;
+ };
+ switch_port2: port@2 {
+ reg = <2>;
+ };
+ switch_port3: port@3 {
+ reg = <3>;
+ };
+ /* internal to-cpu ports */
+ port@4 {
+ reg = <4>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port@5 {
+ reg = <5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ ethernet@0,6 {
+ compatible = "fsl,enetc";
+ reg = <0x000600 0 0 0 0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
};
rcpm: rcpm@1e34040 {

62
target/linux/layerscape/patches-5.4/302-dts-0075-arm64-dts-fsl-ls1028a-Enable-switch-PHYs-on-RDB.patch Normal file
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@ -0,0 +1,62 @@
From aafb63a926b790b64a5ed83377f07b90ec7ba7c0 Mon Sep 17 00:00:00 2001
From: Claudiu Manoil <claudiu.manoil@nxp.com>
Date: Thu, 20 Jun 2019 19:53:55 +0300
Subject: [PATCH] arm64: dts: fsl: ls1028a: Enable switch PHYs on RDB
Just link the switch PHY nodes to the central MDIO
controller PCIe endpoint node on ls1028 (implemented
as PF3) so that PHYs are configurable via MDIO.
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 39 +++++++++++++++++++++++
1 file changed, 39 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -208,6 +208,45 @@
status = "disabled";
};
+&enetc_mdio_pf3 {
+ qsgmii_phy1: ethernet-phy@4 {
+ reg = <0x10>;
+ };
+
+ qsgmii_phy2: ethernet-phy@5 {
+ reg = <0x11>;
+ };
+
+ qsgmii_phy3: ethernet-phy@6 {
+ reg = <0x12>;
+ };
+
+ qsgmii_phy4: ethernet-phy@7 {
+ reg = <0x13>;
+ };
+};
+
+/* l2switch ports */
+&switch_port0 {
+ phy-handle = <&qsgmii_phy1>;
+ phy-connection-type = "qsgmii";
+};
+
+&switch_port1 {
+ phy-handle = <&qsgmii_phy2>;
+ phy-connection-type = "qsgmii";
+};
+
+&switch_port2 {
+ phy-handle = <&qsgmii_phy3>;
+ phy-connection-type = "qsgmii";
+};
+
+&switch_port3 {
+ phy-handle = <&qsgmii_phy4>;
+ phy-connection-type = "qsgmii";
+};
+
&sai4 {
status = "okay";
};

34
target/linux/layerscape/patches-5.4/302-dts-0076-arm64-dts-ls1028a-support-Felix-PF5-INTB-interrupt.patch Normal file
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@ -0,0 +1,34 @@
From 28aa7c7f0da70b7410926ec5f5737e2b78e0cdfa Mon Sep 17 00:00:00 2001
From: Alex Marginean <alexandru.marginean@nxp.com>
Date: Thu, 18 Jul 2019 15:26:03 +0800
Subject: [PATCH] arm64: dts: ls1028a: support Felix/PF5 INTB interrupt
The INTB interrupt includes,
- PTP timestamp ready in timestamp FIFO
- TSN Preemption
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -732,7 +732,6 @@
reg = <0x01 0xf0000000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
- #interrupt-cells = <1>;
msi-parent = <&its>;
device_type = "pci";
bus-range = <0x0 0x0>;
@@ -785,6 +784,8 @@
switch@0,5 {
compatible = "mscc,felix-switch";
reg = <0x000500 0 0 0 0>;
+ /* IEP INT_B */
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
ports {
#address-cells = <1>;

33
target/linux/layerscape/patches-5.4/302-dts-0077-arm64-dts-ls1028a-Add-ethernet-property-for-l2switch.patch Normal file
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@ -0,0 +1,33 @@
From 51efcd436c30e7085b36264771edce03316013d1 Mon Sep 17 00:00:00 2001
From: Claudiu Manoil <claudiu.manoil@nxp.com>
Date: Thu, 1 Aug 2019 19:44:00 +0300
Subject: [PATCH] arm64: dts: ls1028a: Add ethernet property for l2switch CPU
port
This enables the CPU traffic for the l2 switch (aka the
CPU frame injection/ extraction feature).
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -814,6 +814,7 @@
};
port@5 {
reg = <5>;
+ ethernet = <&enetc_port3>;
fixed-link {
speed = <1000>;
full-duplex;
@@ -821,7 +822,7 @@
};
};
};
- ethernet@0,6 {
+ enetc_port3: ethernet@0,6 {
compatible = "fsl,enetc";
reg = <0x000600 0 0 0 0>;
fixed-link {

44
target/linux/layerscape/patches-5.4/302-dts-0078-arm64-dts-fix-endianness-of-rcpm.patch Normal file
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@ -0,0 +1,44 @@
From fdba7c7bc334f72bd8641bbd63f3596ba68650c1 Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Thu, 8 Aug 2019 12:13:02 +0800
Subject: [PATCH] arm64: dts: fix endianness of rcpm
Add little-endian property of rcpm for ls1028a,ls1088a,ls208xa
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 1 +
3 files changed, 3 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -836,6 +836,7 @@
compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x1c>;
#fsl,rcpm-wakeup-cells = <7>;
+ little-endian;
};
ftm_alarm0: timer@2800000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -792,6 +792,7 @@
compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x18>;
#fsl,rcpm-wakeup-cells = <6>;
+ little-endian;
};
ftm_alarm0: timer@2800000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -762,6 +762,7 @@
compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x18>;
#fsl,rcpm-wakeup-cells = <6>;
+ little-endian;
};
ftm_alarm0: timer@2800000 {

45
target/linux/layerscape/patches-5.4/302-dts-0079-arm64-dts-ls1028a-Fix-interrupt-map-property-of-PCIe.patch Normal file
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@ -0,0 +1,45 @@
From e41ad4213ce6742646c9dfed661289e69d5af5c1 Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Fri, 2 Aug 2019 16:42:53 +0800
Subject: [PATCH] arm64: dts: ls1028a: Fix interrupt-map property of PCIe nodes
The current interrupt-map entries lost the 'parent unit address',
it will result in fail to allocate legacy INTx interrupts.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -695,10 +695,10 @@
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -720,10 +720,10 @@
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

23
target/linux/layerscape/patches-5.4/302-dts-0080-arm64-dts-ls1028a-rdb-enable-emmc-hs400-mode.patch Normal file
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@ -0,0 +1,23 @@
From f1f32315bcb6b50e9af701d4504c2cfa11823c98 Mon Sep 17 00:00:00 2001
From: Yinbo Zhu <yinbo.zhu@nxp.com>
Date: Tue, 13 Aug 2019 17:01:44 +0800
Subject: [PATCH] arm64: dts: ls1028a-rdb: enable emmc hs400 mode
This patch is to enable emmc hs400 mode for ls1028ardb
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -93,6 +93,8 @@
&esdhc1 {
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
status = "okay";
};

47
target/linux/layerscape/patches-5.4/302-dts-0081-arm64-dts-lx2160a-add-ftm_alarm0-DT-node.patch Normal file
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@ -0,0 +1,47 @@
From 31301e26a9d72fe2e4ecdf0999e9fda4c6832188 Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Thu, 1 Aug 2019 12:34:33 +0800
Subject: [PATCH] arm64: dts: lx2160a: add ftm_alarm0 DT node
The patch adds ftm_alarm0 DT node for Soc LX2160A
FlexTimer1 module is used to wakeup the system in deep sleep
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -15,6 +15,10 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ rtc1 = &ftm_alarm0;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -769,6 +773,20 @@
timeout-sec = <30>;
};
+ rcpm: rcpm@1e34040 {
+ compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x1c>;
+ #fsl,rcpm-wakeup-cells = <7>;
+ little-endian;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,lx2160a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <0 44 4>;
+ };
+
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;

293
target/linux/layerscape/patches-5.4/302-dts-0082-arm64-dts-lx2160a-add-tmu-device-node.patch Normal file
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@ -0,0 +1,293 @@
From f6233242d21bb4cb973a7dfc61dcfbf6d9a5d22b Mon Sep 17 00:00:00 2001
From: Yuantian Tang <andy.tang@nxp.com>
Date: Mon, 2 Sep 2019 17:45:19 +0800
Subject: [PATCH] arm64: dts: lx2160a: add tmu device node
Add the TMU (Thermal Monitoring Unit) device node to enable
TMU feature.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++++++++++++++++++++----
1 file changed, 92 insertions(+), 16 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/memreserve/ 0x80000000 0x00010000;
@@ -24,7 +25,7 @@
#size-cells = <0>;
// 8 clusters having 2 Cortex-A72 cores each
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -38,9 +39,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -54,9 +56,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@100 {
+ cpu100: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -70,9 +73,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@101 {
+ cpu101: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -86,9 +90,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@200 {
+ cpu200: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -102,9 +107,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@201 {
+ cpu201: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -118,9 +124,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@300 {
+ cpu300: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -134,9 +141,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@301 {
+ cpu301: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -150,9 +158,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@400 {
+ cpu400: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -166,9 +175,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@401 {
+ cpu401: cpu@401 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -182,9 +192,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@500 {
+ cpu500: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -198,9 +209,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@501 {
+ cpu501: cpu@501 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -214,9 +226,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@600 {
+ cpu600: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -230,9 +243,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@601 {
+ cpu601: cpu@601 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -246,9 +260,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@700 {
+ cpu700: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -262,9 +277,10 @@
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
- cpu@701 {
+ cpu701: cpu@701 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -278,6 +294,7 @@
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw15>;
+ #cooling-cells = <2>;
};
cluster0_l2: l2-cache0 {
@@ -422,6 +439,51 @@
clock-output-names = "sysclk";
};
+ thermal-zones {
+ core_thermal1: core-thermal1 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ core_cluster_alert: core-cluster-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ core_cluster_crit: core-cluster-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&core_cluster_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -689,6 +751,20 @@
status = "disabled";
};
+ tmu: tmu@1f80000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f80000 0x0 0x10000>;
+ interrupts = <0 23 0x4>;
+ fsl,tmu-range = <0x800000E6 0x8001017D>;
+ fsl,tmu-calibration =
+ /* Calibration data group 1 */
+ <0x00000000 0x00000035
+ /* Calibration data group 2 */
+ 0x00010001 0x00000154>;
+ little-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
uart0: serial@21c0000 {
compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21c0000 0x0 0x1000>;

42
target/linux/layerscape/patches-5.4/302-dts-0083-arm64-ls1028a-qds-correct-bus-of-rtc.patch Normal file
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@ -0,0 +1,42 @@
From d4c7270a63b1d78b89d91f74d782cce2a2bd9690 Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Wed, 4 Sep 2019 11:39:30 +0800
Subject: [PATCH] arm64: ls1028a-qds: correct bus of rtc
The rtc is on i2c2 bus(hardware), not on i2c1 channel 3,
so correct it
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -169,11 +169,6 @@
vcc-supply = <&sb_3v3>;
};
- rtc@51 {
- compatible = "nxp,pcf2129";
- reg = <0x51>;
- };
-
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x56>;
@@ -217,6 +212,14 @@
};
+&i2c1 {
+ status = "okay";
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ };
+};
+
&enetc_port1 {
phy-handle = <&qds_phy1>;
phy-connection-type = "rgmii-id";

355
target/linux/layerscape/patches-5.4/302-dts-0084-arm64-dts-ls1028a-define-networking-options-for-QDS.patch Normal file
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@ -0,0 +1,355 @@
From 0c767bcfe1b4d940f2889820f12d278cbba764b5 Mon Sep 17 00:00:00 2001
From: Alex Marginean <alexandru.marginean@nxp.com>
Date: Tue, 27 Aug 2019 15:12:00 +0300
Subject: [PATCH] arm64: dts: ls1028a: define networking options for QDS
Defines connectivity for a few serdes protocol combinations (85xx, 65xx,
13xx, 9999, 7777).
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
---
.../boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi | 20 ++++++++
.../boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi | 20 ++++++++
.../boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi | 56 ++++++++++++++++++++
.../boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi | 19 +++++++
.../boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi | 60 ++++++++++++++++++++++
.../boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi | 48 +++++++++++++++++
.../boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi | 44 ++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 27 ++++++++++
8 files changed, 294 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for LS1028A QDS board, serdes 1xxx
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+&mdio_slot1 {
+ slot1_sgmii: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&slot1_sgmii>;
+ phy-connection-type = "usxgmii";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for LS1028A QDS board, serdes 6xxx
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+&mdio_slot1 {
+ slot1_sgmii: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&slot1_sgmii>;
+ phy-connection-type = "2500base-x";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for LS1028A QDS board, serdes 9999
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+&mdio_slot1 {
+ /* two ports on AQR412 */
+ slot1_sxgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ slot1_sxgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&mdio_slot2 {
+ slot2_sxgmii0: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+&mdio_slot3 {
+ slot3_sxgmii0: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+/* l2switch ports */
+&switch_port0 {
+ phy-handle = <&slot1_sxgmii2>;
+ phy-connection-type = "2500base-x";
+};
+
+&switch_port1 {
+ phy-handle = <&slot2_sxgmii0>;
+ phy-connection-type = "2500base-x";
+};
+
+&switch_port2 {
+ phy-handle = <&slot3_sxgmii0>;
+ phy-connection-type = "2500base-x";
+};
+
+&switch_port3 {
+ phy-handle = <&slot1_sxgmii3>;
+ phy-connection-type = "2500base-x";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for LS1028A QDS board, serdes 8xxx
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+&mdio_slot1 {
+ slot1_sgmii: ethernet-phy@1c {
+ /* 1st port on VSC8234 */
+ reg = <0x1c>;
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&slot1_sgmii>;
+ phy-connection-type = "sgmii";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for LS1028A QDS board, serdes 9999
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+&mdio_slot1 {
+ /* VSC8234 */
+ slot1_sgmii0: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ slot1_sgmii1: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+ slot1_sgmii2: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+ slot1_sgmii3: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
+
+&mdio_slot2 {
+ /* VSC8234 */
+ slot2_sgmii0: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ slot2_sgmii1: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+ slot2_sgmii2: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+ slot2_sgmii3: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
+
+/* l2switch ports */
+&switch_port0 {
+ phy-handle = <&slot1_sgmii0>;
+ phy-connection-type = "sgmii";
+};
+
+&switch_port1 {
+ phy-handle = <&slot2_sgmii0>;
+ phy-connection-type = "sgmii";
+};
+
+&switch_port2 {
+ phy-handle = <&slot1_sgmii2>;
+ phy-connection-type = "sgmii";
+};
+
+&switch_port3 {
+ phy-handle = <&slot1_sgmii3>;
+ phy-connection-type = "sgmii";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for LS1028A QDS board, serdes x3xx
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+&mdio_slot2 {
+ /* 4 ports on AQR412 */
+ slot2_qsgmii0: ethernet-phy@0 {
+ reg = <0x0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ slot2_qsgmii1: ethernet-phy@1 {
+ reg = <0x1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ slot2_qsgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ slot2_qsgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+};
+
+/* l2switch ports */
+&switch_port0 {
+ phy-handle = <&slot2_qsgmii0>;
+ phy-connection-type = "usxgmii";
+};
+
+&switch_port1 {
+ phy-handle = <&slot2_qsgmii1>;
+ phy-connection-type = "usxgmii";
+};
+
+&switch_port2 {
+ phy-handle = <&slot2_qsgmii2>;
+ phy-connection-type = "usxgmii";
+};
+
+&switch_port3 {
+ phy-handle = <&slot2_qsgmii3>;
+ phy-connection-type = "usxgmii";
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for LS1028A QDS board, serdes x5xx
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+&mdio_slot2 {
+ /* 4 ports on VSC8514 */
+ slot2_qsgmii0: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+ slot2_qsgmii1: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+ slot2_qsgmii2: ethernet-phy@a {
+ reg = <0xa>;
+ };
+ slot2_qsgmii3: ethernet-phy@b {
+ reg = <0xb>;
+ };
+};
+
+/* l2switch ports */
+&switch_port0 {
+ phy-handle = <&slot2_qsgmii0>;
+ phy-connection-type = "qsgmii";
+};
+
+&switch_port1 {
+ phy-handle = <&slot2_qsgmii1>;
+ phy-connection-type = "qsgmii";
+};
+
+&switch_port2 {
+ phy-handle = <&slot2_qsgmii2>;
+ phy-connection-type = "qsgmii";
+};
+
+&switch_port3 {
+ phy-handle = <&slot2_qsgmii3>;
+ phy-connection-type = "qsgmii";
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -104,6 +104,30 @@
reg = <5>;
};
};
+
+ mdio_slot1: mdio@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ mdio_slot2: mdio@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ mdio_slot3: mdio@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ mdio_slot4: mdio@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
};
};
@@ -259,3 +283,6 @@
edp_num_lanes = <0x4>;
status = "okay";
};
+
+#include "fsl-ls1028a-qds-8xxx.dtsi"
+#include "fsl-ls1028a-qds-x5xx.dtsi"

51
target/linux/layerscape/patches-5.4/302-dts-0085-arm64-dts-LS1028a-rdb-use-Ethernet-PHY-interrupt.patch Normal file
View File

@ -0,0 +1,51 @@
From 3dc3a4c6ac9e8a0940a9974b8fe2da7641bfa3dd Mon Sep 17 00:00:00 2001
From: Alex Marginean <alexandru.marginean@nxp.com>
Date: Thu, 22 Aug 2019 12:47:12 +0300
Subject: [PATCH] arm64: dts: LS1028a-rdb: use Ethernet PHY interrupt
Use the PHY interrupt wired to GPIO pins as part of MDIO WA performance
impact mitigation.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -202,6 +202,8 @@
#size-cells = <0>;
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};
};
@@ -213,18 +215,26 @@
&enetc_mdio_pf3 {
qsgmii_phy1: ethernet-phy@4 {
reg = <0x10>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
qsgmii_phy2: ethernet-phy@5 {
reg = <0x11>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
qsgmii_phy3: ethernet-phy@6 {
reg = <0x12>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
qsgmii_phy4: ethernet-phy@7 {
reg = <0x13>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
};

53
target/linux/layerscape/patches-5.4/302-dts-0086-usb-dwc3-enable-otg-mode-for-dwc3-usb-ip-on-layersca.patch Normal file
View File

@ -0,0 +1,53 @@
From 411bee5b3e729e4dd691051e13f77dfb994e0da8 Mon Sep 17 00:00:00 2001
From: Yinbo Zhu <yinbo.zhu@nxp.com>
Date: Mon, 9 Sep 2019 15:57:52 +0800
Subject: [PATCH] usb: dwc3: enable otg mode for dwc3 usb ip on layerscape
layerscape otg function should be supported HNP SRP and ADP protocol
accroing to rm doc, but dwc3 code not realize it and use id pin to
detect who is host or device(0 is host 1 is device) this patch is to
enable OTG mode on ls1028ardb ls1088ardb and ls1046ardb in dts
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 1 +
3 files changed, 9 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -98,6 +98,10 @@
status = "okay";
};
+&usb1 {
+ dr_mode = "otg";
+};
+
&i2c0 {
status = "okay";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -44,6 +44,10 @@
sd-uhs-sdr12;
};
+&usb1 {
+ dr_mode = "otg";
+};
+
&i2c0 {
status = "okay";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -120,6 +120,7 @@
};
&usb1 {
+ dr_mode = "otg";
status = "okay";
};

29
target/linux/layerscape/patches-5.4/302-dts-0087-arm-dts-ls1021a-fix-that-FlexTimer-cannot-wakeup-sys.patch Normal file
View File

@ -0,0 +1,29 @@
From c221e05b50ca68daf5a20069ee1928171ef43bae Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Sat, 14 Sep 2019 12:59:36 +0800
Subject: [PATCH] arm: dts: ls1021a: fix that FlexTimer cannot wakeup system in
deep sleep
The patch fixes a bug that FlexTimer cannot
wakeup system in deep sleep.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -998,6 +998,12 @@
compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1ee2140 0x0 0x8>;
#fsl,rcpm-wakeup-cells = <2>;
+
+ /*
+ * The second and third entry compose an alt offset
+ * address for IPPDEXPCR1(SCFG_SPARECR8)
+ */
+ fsl,ippdexpcr1-alt-addr = <&scfg 0x0 0x51c>;
};
ftm_alarm0: timer0@29d0000 {

34
target/linux/layerscape/patches-5.4/302-dts-0088-arm64-dts-ls1028a-fix-dwc-pci-over-smmu.patch Normal file
View File

@ -0,0 +1,34 @@
From 127b30b66c3b48ee717ed7335987334e8dc769b5 Mon Sep 17 00:00:00 2001
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Tue, 1 Oct 2019 13:47:11 +0300
Subject: [PATCH] arm64: dts: ls1028a: fix dwc pci over smmu
In order for the dwc controller to work with SMMU it needs the
bootloader to fixup it's iommu-map property. In the current
implementation to bootloader will not perform the fixup if the
property is not already in the device tree with dummy fields.
Add it to fix DWC PCI over SMMU.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -689,6 +689,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -714,6 +715,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

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