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https://github.com/openwrt/openwrt.git
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f0b2fdb82e
1. Remove unnecessary new lines in the dts.
2. Remove duplicate included file "gpio.h" in the device dts.
3. Add missing button labels "reset" and "wps".
4. Unify the format of the reg properties.
5. Add u-boot environment support.
6. Reduce spi clock frequency since the max value suggested by the
chip datasheet is only 25 MHz.
7. Add seama header fixup for DIR-859 A1. Without this header fixup,
u-boot checksum for kernel will fail after the first boot.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
(cherry picked from commit e5d8739aa8)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
153 lines
2.7 KiB
Plaintext
153 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "qca956x.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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keys {
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compatible = "gpio-keys";
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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};
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&pcie {
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status = "okay";
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wifi@0,0 {
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compatible = "qcom,ath10k";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&calibration_ath10k>, <&macaddr_devdata_94>;
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nvmem-cell-names = "calibration", "mac-address-ascii";
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};
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};
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&spi {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootloader";
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reg = <0x000000 0x040000>;
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read-only;
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};
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partition@40000 {
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compatible = "u-boot,env";
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label = "bdcfg";
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reg = <0x040000 0x010000>;
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};
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partition@50000 {
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label = "devdata";
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reg = <0x050000 0x010000>;
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read-only;
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_devdata_94: macaddr@94 {
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reg = <0x94 0x11>;
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};
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macaddr_devdata_b0: macaddr@b0 {
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reg = <0xb0 0x11>;
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};
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};
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partition@60000 {
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label = "devconf";
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reg = <0x060000 0x010000>;
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read-only;
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};
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partition@70000 {
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compatible = "seama";
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label = "firmware";
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reg = <0x070000 0xf80000>;
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};
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partition@ff0000 {
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label = "art";
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reg = <0xff0000 0x010000>;
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read-only;
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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calibration_ath9k: calibration@1000 {
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reg = <0x1000 0x440>;
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};
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calibration_ath10k: calibration@5000 {
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reg = <0x5000 0x844>;
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};
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};
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};
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};
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};
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&mdio0 {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "sgmii";
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qca,mib-poll-interval = <500>;
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reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
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qca,ar8327-initvals = <
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0x04 0x00080080 /* PORT0 PAD MODE CTRL */
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0x10 0x81000080 /* POWER_ON_STRAP */
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0x50 0xcc35cc35 /* LED_CTRL0 */
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0x54 0xcb37cb37 /* LED_CTRL1 */
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0x58 0x00000000 /* LED_CTRL2 */
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0x5c 0x00f3cf00 /* LED_CTRL3 */
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0x7c 0x0000007e /* PORT0_STATUS */
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>;
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};
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};
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ð0 {
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status = "okay";
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pll-data = <0x03000101 0x00000101 0x00001919>;
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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};
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&wmac {
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status = "okay";
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nvmem-cells = <&calibration_ath9k>, <&macaddr_devdata_b0>;
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nvmem-cell-names = "calibration", "mac-address-ascii";
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};
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