mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 09:12:39 +00:00
cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
44 lines
1.2 KiB
Diff
44 lines
1.2 KiB
Diff
From e0afa16cad94b26e13d673647b781dd336cb30bc Mon Sep 17 00:00:00 2001
|
|
From: Wen He <wen.he_1@nxp.com>
|
|
Date: Mon, 14 Oct 2019 14:25:42 +0800
|
|
Subject: [PATCH] arm64: dts: ls1028a: Add properties for HD Display controller
|
|
node
|
|
|
|
The HD Display controller includes DP TX CTRL and DPHY, their offers
|
|
multi-protocol support of standards such as DisplayPort and eDP, with
|
|
one of these standards supported at a time.
|
|
|
|
This patch enables the HD Display controller driver on the LS1028A.
|
|
|
|
Signed-off-by: Wen He <wen.he_1@nxp.com>
|
|
---
|
|
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 16 ++++++++++++++++
|
|
1 file changed, 16 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
|
|
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
|
|
@@ -856,7 +856,23 @@
|
|
|
|
port {
|
|
dp0_out: endpoint {
|
|
+ remote-endpoint = <&dp1_out>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
|
|
+ hdptx0: display@f200000 {
|
|
+ compatible = "cdn,ls1028a-dp";
|
|
+ reg = <0x0 0xf200000 0x0 0xfffff>;
|
|
+ interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clockgen 2 2>, <&clockgen 2 2>, <&clockgen 2 2>,
|
|
+ <&clockgen 2 2>, <&clockgen 2 2>, <&dpclk>;
|
|
+ clock-names = "clk_core", "pclk", "sclk",
|
|
+ "cclk", "clk_vif", "clk_pxl";
|
|
+
|
|
+ port {
|
|
+ dp1_out: endpoint {
|
|
+ remote-endpoint = <&dp0_out>;
|
|
};
|
|
};
|
|
};
|