mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 09:12:39 +00:00
cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
63 lines
1.3 KiB
Diff
63 lines
1.3 KiB
Diff
From aafb63a926b790b64a5ed83377f07b90ec7ba7c0 Mon Sep 17 00:00:00 2001
|
|
From: Claudiu Manoil <claudiu.manoil@nxp.com>
|
|
Date: Thu, 20 Jun 2019 19:53:55 +0300
|
|
Subject: [PATCH] arm64: dts: fsl: ls1028a: Enable switch PHYs on RDB
|
|
|
|
Just link the switch PHY nodes to the central MDIO
|
|
controller PCIe endpoint node on ls1028 (implemented
|
|
as PF3) so that PHYs are configurable via MDIO.
|
|
|
|
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
|
|
---
|
|
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 39 +++++++++++++++++++++++
|
|
1 file changed, 39 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
|
|
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
|
|
@@ -208,6 +208,45 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+&enetc_mdio_pf3 {
|
|
+ qsgmii_phy1: ethernet-phy@4 {
|
|
+ reg = <0x10>;
|
|
+ };
|
|
+
|
|
+ qsgmii_phy2: ethernet-phy@5 {
|
|
+ reg = <0x11>;
|
|
+ };
|
|
+
|
|
+ qsgmii_phy3: ethernet-phy@6 {
|
|
+ reg = <0x12>;
|
|
+ };
|
|
+
|
|
+ qsgmii_phy4: ethernet-phy@7 {
|
|
+ reg = <0x13>;
|
|
+ };
|
|
+};
|
|
+
|
|
+/* l2switch ports */
|
|
+&switch_port0 {
|
|
+ phy-handle = <&qsgmii_phy1>;
|
|
+ phy-connection-type = "qsgmii";
|
|
+};
|
|
+
|
|
+&switch_port1 {
|
|
+ phy-handle = <&qsgmii_phy2>;
|
|
+ phy-connection-type = "qsgmii";
|
|
+};
|
|
+
|
|
+&switch_port2 {
|
|
+ phy-handle = <&qsgmii_phy3>;
|
|
+ phy-connection-type = "qsgmii";
|
|
+};
|
|
+
|
|
+&switch_port3 {
|
|
+ phy-handle = <&qsgmii_phy4>;
|
|
+ phy-connection-type = "qsgmii";
|
|
+};
|
|
+
|
|
&sai4 {
|
|
status = "okay";
|
|
};
|