Daniel Golle
ecc9d0195b
mediatek: mt7988: fix clk for 2nd PCIe port ...
Due to what seems to be an undocumented oddity in MediaTek's MT7988
SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
This currently leads to PCIe port 2 not working in Linux.
Reflect the apparent relationship in the clk driver to make sure PCIe
port 2 of the MT7988 SoC works.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2024-03-11 19:14:14 +00:00
2024-02-26 13:19:26 +01:00
2024-03-02 14:08:07 +01:00
2023-05-12 13:02:43 +02:00
2024-01-19 21:24:44 +01:00
2024-03-07 19:30:54 +01:00
2024-03-09 20:00:11 +01:00
2024-03-05 00:23:59 +01:00
2024-01-06 10:53:39 +01:00
2024-03-07 19:30:54 +01:00
2023-10-27 19:43:06 +01:00
2024-03-10 20:26:07 +01:00
2024-03-05 00:23:59 +01:00
2024-01-06 12:52:49 +01:00
2024-03-11 19:14:14 +00:00
2024-02-24 19:25:02 +01:00
2024-03-09 20:00:11 +01:00
2024-02-23 18:05:09 +01:00
2023-12-09 14:45:50 +01:00
2024-02-29 23:01:38 +01:00
2024-03-08 14:49:09 +01:00
2024-03-01 18:29:09 +01:00
2024-02-03 04:35:25 +00:00
2024-03-11 19:14:14 +00:00
2024-03-08 17:24:14 +01:00
2024-03-02 14:21:20 +01:00
2023-07-01 12:54:30 +02:00
2024-02-07 14:48:41 +01:00
2024-03-07 19:30:54 +01:00
2024-02-13 19:05:48 +01:00
2024-01-01 02:34:48 +01:00
2023-10-31 17:33:28 +01:00
2023-12-02 14:06:56 +02:00
2024-03-05 06:34:35 +01:00
2024-03-10 16:32:14 +09:00
2024-02-18 09:56:45 +01:00
2024-02-25 12:36:02 +08:00
2023-11-19 16:46:24 +01:00
2024-03-10 18:21:46 +01:00
2023-12-19 16:02:05 +01:00
2023-05-12 13:02:43 +02:00
2023-09-23 13:10:28 +02:00
2023-12-23 07:52:05 +00:00
2023-05-10 19:01:45 +02:00
2024-02-08 23:04:55 +01:00
ecc9d0195b