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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
294 lines
7.2 KiB
Diff
294 lines
7.2 KiB
Diff
From f6233242d21bb4cb973a7dfc61dcfbf6d9a5d22b Mon Sep 17 00:00:00 2001
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From: Yuantian Tang <andy.tang@nxp.com>
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Date: Mon, 2 Sep 2019 17:45:19 +0800
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Subject: [PATCH] arm64: dts: lx2160a: add tmu device node
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Add the TMU (Thermal Monitoring Unit) device node to enable
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TMU feature.
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Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++++++++++++++++++++----
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1 file changed, 92 insertions(+), 16 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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@@ -6,6 +6,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/thermal/thermal.h>
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/memreserve/ 0x80000000 0x00010000;
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@@ -24,7 +25,7 @@
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#size-cells = <0>;
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// 8 clusters having 2 Cortex-A72 cores each
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- cpu@0 {
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+ cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -38,9 +39,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster0_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@1 {
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+ cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -54,9 +56,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster0_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@100 {
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+ cpu100: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -70,9 +73,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster1_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@101 {
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+ cpu101: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -86,9 +90,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster1_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@200 {
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+ cpu200: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -102,9 +107,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster2_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@201 {
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+ cpu201: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -118,9 +124,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster2_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@300 {
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+ cpu300: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -134,9 +141,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster3_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@301 {
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+ cpu301: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -150,9 +158,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster3_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@400 {
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+ cpu400: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -166,9 +175,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster4_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@401 {
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+ cpu401: cpu@401 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -182,9 +192,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster4_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@500 {
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+ cpu500: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -198,9 +209,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster5_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@501 {
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+ cpu501: cpu@501 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -214,9 +226,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster5_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@600 {
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+ cpu600: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -230,9 +243,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster6_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@601 {
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+ cpu601: cpu@601 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -246,9 +260,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster6_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@700 {
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+ cpu700: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -262,9 +277,10 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster7_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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- cpu@701 {
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+ cpu701: cpu@701 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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@@ -278,6 +294,7 @@
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i-cache-sets = <192>;
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next-level-cache = <&cluster7_l2>;
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cpu-idle-states = <&cpu_pw15>;
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+ #cooling-cells = <2>;
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};
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cluster0_l2: l2-cache0 {
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@@ -422,6 +439,51 @@
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clock-output-names = "sysclk";
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};
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+ thermal-zones {
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+ core_thermal1: core-thermal1 {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <5000>;
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+ thermal-sensors = <&tmu 0>;
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+
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+ trips {
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+ core_cluster_alert: core-cluster-alert {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ core_cluster_crit: core-cluster-crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&core_cluster_alert>;
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+ cooling-device =
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+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+ };
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+ };
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+
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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@@ -689,6 +751,20 @@
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status = "disabled";
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};
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+ tmu: tmu@1f80000 {
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+ compatible = "fsl,qoriq-tmu";
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+ reg = <0x0 0x1f80000 0x0 0x10000>;
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+ interrupts = <0 23 0x4>;
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+ fsl,tmu-range = <0x800000E6 0x8001017D>;
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+ fsl,tmu-calibration =
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+ /* Calibration data group 1 */
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+ <0x00000000 0x00000035
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+ /* Calibration data group 2 */
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+ 0x00010001 0x00000154>;
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+ little-endian;
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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uart0: serial@21c0000 {
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compatible = "arm,sbsa-uart","arm,pl011";
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reg = <0x0 0x21c0000 0x0 0x1000>;
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