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4d213b2ae2
The redundant xtal clock source caused clock registration failure. Link: https://lore.kernel.org/all/20250108093636.265033-1-sergio.paracuellos@gmail.com/ Fixes: https://github.com/openwrt/openwrt/issues/17677 Signed-off-by: Shiji Yang <yangshiji66@qq.com> Link: https://github.com/openwrt/openwrt/pull/17830 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> (cherry picked from commit cfca9d689459426a119edbc02ecb7c778a3c2b77)
59 lines
1.5 KiB
Diff
59 lines
1.5 KiB
Diff
From ef57412d070fe663a66a5473ffc708bd89671259 Mon Sep 17 00:00:00 2001
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From: Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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Date: Sun, 2 Feb 2025 17:10:14 +0800
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Subject: [PATCH] mips: ralink: update CPU clock index
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Some clock indexes have been reorganized in commit d34db686a3d7
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("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs").
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Update CPU clock index to match the clock driver changes.
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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Co-authored-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
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---
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arch/mips/ralink/clk.c | 11 ++---------
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1 file changed, 2 insertions(+), 9 deletions(-)
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--- a/arch/mips/ralink/clk.c
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+++ b/arch/mips/ralink/clk.c
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@@ -19,27 +19,22 @@
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static const char *clk_cpu(int *idx)
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{
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+ *idx = 1;
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+
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switch (ralink_soc) {
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case RT2880_SOC:
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- *idx = 0;
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return "ralink,rt2880-sysc";
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case RT3883_SOC:
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- *idx = 0;
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return "ralink,rt3883-sysc";
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case RT305X_SOC_RT3050:
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- *idx = 0;
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return "ralink,rt3050-sysc";
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case RT305X_SOC_RT3052:
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- *idx = 0;
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return "ralink,rt3052-sysc";
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case RT305X_SOC_RT3350:
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- *idx = 1;
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return "ralink,rt3350-sysc";
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case RT305X_SOC_RT3352:
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- *idx = 1;
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return "ralink,rt3352-sysc";
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case RT305X_SOC_RT5350:
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- *idx = 1;
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return "ralink,rt5350-sysc";
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case MT762X_SOC_MT7620A:
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*idx = 2;
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@@ -48,10 +43,8 @@ static const char *clk_cpu(int *idx)
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*idx = 2;
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return "ralink,mt7620-sysc";
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case MT762X_SOC_MT7628AN:
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- *idx = 1;
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return "ralink,mt7628-sysc";
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case MT762X_SOC_MT7688:
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- *idx = 1;
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return "ralink,mt7688-sysc";
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default:
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*idx = -1;
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