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ramips: fix xtal clock registration issue on RT3883

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The redundant xtal clock source caused clock registration failure.

Link: https://lore.kernel.org/all/20250108093636.265033-1-sergio.paracuellos@gmail.com/
Fixes: https://github.com/openwrt/openwrt/issues/17677
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Link: https://github.com/openwrt/openwrt/pull/17830
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit cfca9d689459426a119edbc02ecb7c778a3c2b77)
This commit is contained in:
Shiji Yang 2025-02-02 16:00:54 +08:00 committed by Hauke Mehrtens
parent c1d5de0c59
commit 4d213b2ae2
3 changed files with 96 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
target/linux/ramips/dts/rt3883.dtsi
View File

@ -51,7 +51,7 @@
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
clocks = <&sysc 5>;
clocks = <&sysc 4>;
interrupt-parent = <&intc>;
interrupts = <1>;
@ -61,7 +61,7 @@
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
clocks = <&sysc 6>;
clocks = <&sysc 5>;
resets = <&sysc 8>;
reset-names = "wdt";
@ -93,7 +93,7 @@
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
clocks = <&sysc 7>;
clocks = <&sysc 6>;
resets = <&sysc 12>;
@ -187,7 +187,7 @@
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
clocks = <&sysc 8>;
clocks = <&sysc 7>;
resets = <&sysc 16>;
reset-names = "i2c";
@ -205,7 +205,7 @@
compatible = "ralink,rt3883-i2s";
reg = <0xa00 0x100>;
clocks = <&sysc 9>;
clocks = <&sysc 8>;
resets = <&sysc 17>;
reset-names = "i2s";
@ -229,7 +229,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&sysc 10>;
clocks = <&sysc 9>;
resets = <&sysc 18>;
reset-names = "spi";
@ -246,7 +246,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&sysc 11>;
clocks = <&sysc 10>;
resets = <&sysc 18>;
reset-names = "spi";
@ -261,7 +261,7 @@
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
clocks = <&sysc 12>;
clocks = <&sysc 11>;
resets = <&sysc 19>;
@ -343,7 +343,7 @@
#size-cells = <0>;
reg = <0x10100000 0x10000>;
clocks = <&sysc 13>;
clocks = <&sysc 12>;
resets = <&sysc 21>;
reset-names = "fe";
@ -463,7 +463,7 @@
compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
reg = <0x10180000 0x40000>;
clocks = <&sysc 14>;
clocks = <&sysc 13>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;

28
target/linux/ramips/patches-6.6/003-v6.14-clk-ralink-mtmips-remove-duplicated-xtal-clock-for-Ralink.patch Normal file
View File

@ -0,0 +1,28 @@
From 830d8062d25581cf0beaa334486eea06834044da Mon Sep 17 00:00:00 2001
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date: Wed, 8 Jan 2025 10:36:36 +0100
Subject: [PATCH] clk: ralink: mtmips: remove duplicated 'xtal' clock for
Ralink SoC RT3883
Ralink SoC RT3883 has already 'xtal' defined as a base clock so there is no
need to redefine it again in fixed clocks section. Hence, remove the duplicate
one from there.
Fixes: d34db686a3d7 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20250108093636.265033-1-sergio.paracuellos@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/ralink/clk-mtmips.c | 1 -
1 file changed, 1 deletion(-)
--- a/drivers/clk/ralink/clk-mtmips.c
+++ b/drivers/clk/ralink/clk-mtmips.c
@@ -266,7 +266,6 @@ err_clk_unreg:
}
static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
- CLK_FIXED("xtal", NULL, 40000000),
CLK_FIXED("periph", "xtal", 40000000)
};

58
target/linux/ramips/patches-6.6/100-mips-ralink-update-CPU-clock-index.patch Normal file
View File

@ -0,0 +1,58 @@
From ef57412d070fe663a66a5473ffc708bd89671259 Mon Sep 17 00:00:00 2001
From: Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Date: Sun, 2 Feb 2025 17:10:14 +0800
Subject: [PATCH] mips: ralink: update CPU clock index
Some clock indexes have been reorganized in commit d34db686a3d7
("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs").
Update CPU clock index to match the clock driver changes.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Co-authored-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
---
arch/mips/ralink/clk.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -19,27 +19,22 @@
static const char *clk_cpu(int *idx)
{
+ *idx = 1;
+
switch (ralink_soc) {
case RT2880_SOC:
- *idx = 0;
return "ralink,rt2880-sysc";
case RT3883_SOC:
- *idx = 0;
return "ralink,rt3883-sysc";
case RT305X_SOC_RT3050:
- *idx = 0;
return "ralink,rt3050-sysc";
case RT305X_SOC_RT3052:
- *idx = 0;
return "ralink,rt3052-sysc";
case RT305X_SOC_RT3350:
- *idx = 1;
return "ralink,rt3350-sysc";
case RT305X_SOC_RT3352:
- *idx = 1;
return "ralink,rt3352-sysc";
case RT305X_SOC_RT5350:
- *idx = 1;
return "ralink,rt5350-sysc";
case MT762X_SOC_MT7620A:
*idx = 2;
@@ -48,10 +43,8 @@ static const char *clk_cpu(int *idx)
*idx = 2;
return "ralink,mt7620-sysc";
case MT762X_SOC_MT7628AN:
- *idx = 1;
return "ralink,mt7628-sysc";
case MT762X_SOC_MT7688:
- *idx = 1;
return "ralink,mt7688-sysc";
default:
*idx = -1;