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2b1c6b21b5
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Also adds support for Raspberry Pi Compute Module 3 (untested). Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
128 lines
3.9 KiB
Diff
128 lines
3.9 KiB
Diff
From e34586ca8f6b346d1ee37230f26c7ad44ca15786 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
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Date: Fri, 12 Jun 2015 19:01:05 +0200
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Subject: [PATCH] irqchip: bcm2835: Add FIQ support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add a duplicate irq range with an offset on the hwirq's so the
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driver can detect that enable_fiq() is used.
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Tested with downstream dwc_otg USB controller driver.
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Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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Acked-by: Stephen Warren <swarren@wwwdotorg.org>
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---
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arch/arm/mach-bcm/Kconfig | 1 +
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drivers/irqchip/irq-bcm2835.c | 51 ++++++++++++++++++++++++++++++++++++++-----
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2 files changed, 47 insertions(+), 5 deletions(-)
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--- a/arch/arm/mach-bcm/Kconfig
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+++ b/arch/arm/mach-bcm/Kconfig
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@@ -128,6 +128,7 @@ config ARCH_BCM2835
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select ARM_ERRATA_411920
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select ARM_TIMER_SP804
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select CLKSRC_OF
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+ select FIQ
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select PINCTRL
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select PINCTRL_BCM2835
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help
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--- a/drivers/irqchip/irq-bcm2835.c
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+++ b/drivers/irqchip/irq-bcm2835.c
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@@ -55,7 +55,7 @@
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#include <asm/mach/irq.h>
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/* Put the bank and irq (32 bits) into the hwirq */
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-#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
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+#define MAKE_HWIRQ(b, n) (((b) << 5) | (n))
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#define HWIRQ_BANK(i) (i >> 5)
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#define HWIRQ_BIT(i) BIT(i & 0x1f)
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@@ -71,9 +71,13 @@
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| SHORTCUT1_MASK | SHORTCUT2_MASK)
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#define REG_FIQ_CONTROL 0x0c
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+#define REG_FIQ_ENABLE 0x80
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+#define REG_FIQ_DISABLE 0
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#define NR_BANKS 3
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#define IRQS_PER_BANK 32
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+#define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0)
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+#define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))
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static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
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static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
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@@ -98,14 +102,38 @@ static void __exception_irq_entry bcm283
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struct pt_regs *regs);
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static void bcm2836_chained_handle_irq(struct irq_desc *desc);
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+static inline unsigned int hwirq_to_fiq(unsigned long hwirq)
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+{
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+ hwirq -= NUMBER_IRQS;
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+ /*
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+ * The hwirq numbering used in this driver is:
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+ * BASE (0-7) GPU1 (32-63) GPU2 (64-95).
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+ * This differ from the one used in the FIQ register:
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+ * GPU1 (0-31) GPU2 (32-63) BASE (64-71)
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+ */
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+ if (hwirq >= 32)
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+ return hwirq - 32;
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+
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+ return hwirq + 64;
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+}
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+
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static void armctrl_mask_irq(struct irq_data *d)
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{
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- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
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+ if (d->hwirq >= NUMBER_IRQS)
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+ writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
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+ else
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+ writel_relaxed(HWIRQ_BIT(d->hwirq),
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+ intc.disable[HWIRQ_BANK(d->hwirq)]);
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}
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static void armctrl_unmask_irq(struct irq_data *d)
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{
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- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
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+ if (d->hwirq >= NUMBER_IRQS)
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+ writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
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+ intc.base + REG_FIQ_CONTROL);
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+ else
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+ writel_relaxed(HWIRQ_BIT(d->hwirq),
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+ intc.enable[HWIRQ_BANK(d->hwirq)]);
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}
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static struct irq_chip armctrl_chip = {
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@@ -151,8 +179,9 @@ static int __init armctrl_of_init(struct
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panic("%s: unable to map IC registers\n",
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node->full_name);
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- intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
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- &armctrl_ops, NULL);
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+ intc.base = base;
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+ intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
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+ &armctrl_ops, NULL);
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if (!intc.domain)
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panic("%s: unable to create IRQ domain\n", node->full_name);
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@@ -182,6 +211,18 @@ static int __init armctrl_of_init(struct
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set_handle_irq(bcm2835_handle_irq);
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}
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+ /* Make a duplicate irq range which is used to enable FIQ */
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+ for (b = 0; b < NR_BANKS; b++) {
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+ for (i = 0; i < bank_irqs[b]; i++) {
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+ irq = irq_create_mapping(intc.domain,
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+ MAKE_HWIRQ(b, i) + NUMBER_IRQS);
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+ BUG_ON(irq <= 0);
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+ irq_set_chip(irq, &armctrl_chip);
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+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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+ }
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+ }
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+ init_FIQ(FIQ_START);
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+
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return 0;
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}
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