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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
155 lines
5.7 KiB
Diff
155 lines
5.7 KiB
Diff
From 861a32edce13ccba86647507fefcfd4910972dd7 Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Thu, 14 Nov 2019 17:03:22 +0200
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Subject: [PATCH] net: mscc: ocelot: move invariant configs out of adjust_link
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It doesn't make sense to rewrite all these registers every time the PHY
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library notifies us about a link state change.
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In a future patch we will customize the MTU for the CPU port, and since
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the MTU was previously configured from adjust_link, if we don't make
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this change, its value would have got overridden.
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mscc/ocelot.c | 85 +++++++++++++++++++-------------------
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1 file changed, 43 insertions(+), 42 deletions(-)
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--- a/drivers/net/ethernet/mscc/ocelot.c
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+++ b/drivers/net/ethernet/mscc/ocelot.c
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@@ -408,7 +408,7 @@ static void ocelot_adjust_link(struct oc
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struct phy_device *phydev)
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{
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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- int speed, atop_wm, mode = 0;
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+ int speed, mode = 0;
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switch (phydev->speed) {
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case SPEED_10:
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@@ -440,32 +440,9 @@ static void ocelot_adjust_link(struct oc
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ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
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mode, DEV_MAC_MODE_CFG);
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- /* Set MAC IFG Gaps
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- * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
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- * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
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- */
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- ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
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- DEV_MAC_IFG_CFG);
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-
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- /* Load seed (0) and set MAC HDX late collision */
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- ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
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- DEV_MAC_HDX_CFG_SEED_LOAD,
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- DEV_MAC_HDX_CFG);
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- mdelay(1);
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- ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
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- DEV_MAC_HDX_CFG);
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-
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if (ocelot->ops->pcs_init)
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ocelot->ops->pcs_init(ocelot, port);
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- /* Set Max Length and maximum tags allowed */
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- ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
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- DEV_MAC_MAXLEN_CFG);
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- ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
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- DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
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- DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
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- DEV_MAC_TAGS_CFG);
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-
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/* Enable MAC module */
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ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
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DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
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@@ -475,22 +452,10 @@ static void ocelot_adjust_link(struct oc
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ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
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DEV_CLOCK_CFG);
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- /* Set SMAC of Pause frame (00:00:00:00:00:00) */
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- ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
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- ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
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-
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/* No PFC */
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ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
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ANA_PFC_PFC_CFG, port);
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- /* Set Pause WM hysteresis
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- * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
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- * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
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- */
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- ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
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- SYS_PAUSE_CFG_PAUSE_STOP(101) |
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- SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
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-
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/* Core: Enable port for frame transfer */
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ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
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QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
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@@ -505,12 +470,6 @@ static void ocelot_adjust_link(struct oc
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SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
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SYS_MAC_FC_CFG, port);
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ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
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-
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- /* Tail dropping watermark */
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- atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
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- ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
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- SYS_ATOP, port);
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- ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
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}
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static void ocelot_port_adjust_link(struct net_device *dev)
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@@ -2145,11 +2104,53 @@ static int ocelot_init_timestamp(struct
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static void ocelot_init_port(struct ocelot *ocelot, int port)
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{
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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+ int atop_wm;
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INIT_LIST_HEAD(&ocelot_port->skbs);
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/* Basic L2 initialization */
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+ /* Set MAC IFG Gaps
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+ * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
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+ * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
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+ */
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+ ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
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+ DEV_MAC_IFG_CFG);
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+
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+ /* Load seed (0) and set MAC HDX late collision */
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+ ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
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+ DEV_MAC_HDX_CFG_SEED_LOAD,
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+ DEV_MAC_HDX_CFG);
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+ mdelay(1);
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+ ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
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+ DEV_MAC_HDX_CFG);
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+
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+ /* Set Max Length and maximum tags allowed */
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+ ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
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+ DEV_MAC_MAXLEN_CFG);
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+ ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
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+ DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
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+ DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
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+ DEV_MAC_TAGS_CFG);
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+
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+ /* Set SMAC of Pause frame (00:00:00:00:00:00) */
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+ ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
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+ ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
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+
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+ /* Set Pause WM hysteresis
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+ * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
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+ * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
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+ */
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+ ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
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+ SYS_PAUSE_CFG_PAUSE_STOP(101) |
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+ SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
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+
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+ /* Tail dropping watermark */
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+ atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
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+ ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
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+ SYS_ATOP, port);
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+ ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
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+
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/* Drop frames with multicast source address */
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ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
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ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
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