openwrt/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts
Patricia Lee 907e9e0bd3 mediatek: add support for Cetron CT3003
**Hardware specification:**

- SoC: MediaTek MT7981B 2x A53
- Flash: ESMT F50L1G41LB 128MB
- RAM: Nanya NT5CC128M16JR-EK 256MB
- Ethernet: 4 x 10/100/1000 Mbps
- Switch: MediaTek MT7531AE
- WiFi: MediaTek MT7976C
- Button: Reset, Mesh
- Power: DC 12V 1A
- UART: 3.3v, 115200n8
  | Layout:   |
  | :-------- |
  | <Antenna> |
  | VCC       |
  | GND       |
  | Tx        |
  | Rx        |

**Flash instructions:**

1. Rename `openwrt-mediatek-filogic-cetron_ct3003-squashfs-factory.bin` to `factory.bin`.
2. Upload the `factory.bin` using the device's Web interface.
3. Click the upgrade button and wait for the process to finish.
4. Access the OpenWrt interface using the same password.
5. Use the 'Restore' function to reset the firmware to its initial state.

**Notes:**

If you plan to recovery the stock firmware in the future, it's advisable
to connect the device via the serial port and enter failsafe mode to
back up all the MTD partitions before proceeding the steps above.

Signed-off-by: Patricia Lee <patricialee320@gmail.com>
2023-09-08 23:17:26 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "mt7981.dtsi"
/ {
model = "Cetron CT3003";
compatible = "cetron,ct3003", "mediatek,mt7981";
aliases {
serial0 = &uart0;
led-boot = &led_status_red;
led-failsafe = &led_status_red;
led-running = &led_status_green;
led-upgrade = &led_status_green;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0 0x40000000 0 0x10000000>;
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";
led_status_red: led_status_red {
label = "red:status";
gpios = <&pio 3 GPIO_ACTIVE_LOW>;
};
led_status_green: led_status_green {
label = "green:status";
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
&mdio_bus {
switch: switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand@0 {
compatible = "spi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;
partition@0 {
label = "BL2";
reg = <0x0000000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
partition@180000 {
label = "art";
reg = <0x0180000 0x0100000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
};
factory: partition@280000 {
label = "Factory";
reg = <0x0280000 0x0100000>;
read-only;
};
partition@380000 {
label = "FIP";
reg = <0x0380000 0x0200000>;
read-only;
};
partition@580000 {
label = "ubi";
reg = <0x0580000 0x2000000>;
};
partition@2580000 {
label = "ubi_backup";
reg = <0x2580000 0x2000000>;
};
partition@4580000 {
label = "Config_backup";
reg = <0x4580000 0x0400000>;
};
};
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "wan";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
};