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c60dd7bef9
The patches in the ath79 target have not been sorted for a long time and they are very chaotic now. This patch sorts them again according to the OpenWrt naming rules[1], so that we can better manage them. [1] https://openwrt.org/docs/guide-developer/toolchain/use-patches-with-buildsystem#naming_patches Signed-off-by: Shiji Yang <yangshiji66@qq.com>
131 lines
4.5 KiB
Diff
131 lines
4.5 KiB
Diff
From: David Bauer <mail@david-bauer.net>
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Date: Sat, 11 Apr 2020 14:03:12 +0200
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Subject: MIPS: pci-ar724x: add QCA9550 reset sequence
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The QCA9550 family of SoCs have a slightly different reset
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sequence compared to older chips.
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Normally the bootloader performs this sequence, however
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some bootloader implementation expect the operating system
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to clear the reset.
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Also get the resets from OF to support handling of the second
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PCIe root-complex on the QCA9558.
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Signed-off-by: David Bauer <mail@david-bauer.net>
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -390,6 +390,7 @@
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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+#define QCA955X_PLL_PCIE_CONFIG_REG 0x0c
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#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
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#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
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#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
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@@ -475,6 +476,9 @@
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#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
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#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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+#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD BIT(30)
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+#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS BIT(16)
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+
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#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
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#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
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#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -8,6 +8,7 @@
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#include <linux/irq.h>
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#include <linux/pci.h>
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+#include <linux/reset.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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@@ -55,6 +56,9 @@ struct ar724x_pci_controller {
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struct irq_domain *domain;
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struct resource io_res;
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struct resource mem_res;
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+
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+ struct reset_control *hc_reset;
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+ struct reset_control *phy_reset;
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};
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static struct irq_chip ar724x_pci_irq_chip;
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@@ -340,18 +344,30 @@ static void ar724x_pci_hw_init(struct ar
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int wait = 0;
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/* deassert PCIe host controller and PCIe PHY reset */
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- ath79_device_reset_clear(AR724X_RESET_PCIE);
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- ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
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+ reset_control_deassert(apc->hc_reset);
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+ reset_control_deassert(apc->phy_reset);
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- /* remove the reset of the PCIE PLL */
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- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
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- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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-
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- /* deassert bypass for the PCIE PLL */
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- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
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- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+ if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) {
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+ /* remove the reset of the PCIE PLL */
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+ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
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+ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD;
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+ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
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+
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+ /* deassert bypass for the PCIE PLL */
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+ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
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+ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS;
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+ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
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+ } else {
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+ /* remove the reset of the PCIE PLL */
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+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
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+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+
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+ /* deassert bypass for the PCIE PLL */
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+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
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+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+ }
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/* set PCIE Application Control to ready */
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app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
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@@ -395,6 +411,14 @@ static int ar724x_pci_probe(struct platf
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if (apc->irq < 0)
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return -EINVAL;
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+ apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc");
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+ if (IS_ERR(apc->hc_reset))
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+ return PTR_ERR(apc->hc_reset);
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+
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+ apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy");
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+ if (IS_ERR(apc->phy_reset))
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+ return PTR_ERR(apc->phy_reset);
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+
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apc->np = pdev->dev.of_node;
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apc->pci_controller.pci_ops = &ar724x_pci_ops;
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apc->pci_controller.io_resource = &apc->io_res;
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@@ -405,7 +429,7 @@ static int ar724x_pci_probe(struct platf
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* Do the full PCIE Root Complex Initialization Sequence if the PCIe
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* host controller is in reset.
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*/
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- if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
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+ if (reset_control_status(apc->hc_reset))
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ar724x_pci_hw_init(apc);
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apc->link_up = ar724x_pci_check_link(apc);
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@@ -423,6 +447,7 @@ static int ar724x_pci_probe(struct platf
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static const struct of_device_id ar724x_pci_ids[] = {
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{ .compatible = "qcom,ar7240-pci" },
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+ { .compatible = "qcom,qca9550-pci" },
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{},
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};
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