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ath79: rename and sort patches by OpenWrt naming rules
The patches in the ath79 target have not been sorted for a long time and they are very chaotic now. This patch sorts them again according to the OpenWrt naming rules[1], so that we can better manage them. [1] https://openwrt.org/docs/guide-developer/toolchain/use-patches-with-buildsystem#naming_patches Signed-off-by: Shiji Yang <yangshiji66@qq.com>
This commit is contained in:
Shiji Yang
David Bauer
parent
496280ef4e
commit
c60dd7bef9
@ -38,7 +38,7 @@ Signed-off-by: Wenli Looi <wlooi@ucalgary.ca>
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chip = "9343";
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -867,6 +867,7 @@
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@@ -862,6 +862,7 @@
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#define REV_ID_MAJOR_QCA9558 0x1130
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#define REV_ID_MAJOR_TP9343 0x0150
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#define REV_ID_MAJOR_QCA956X 0x1150
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@ -16,7 +16,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -391,6 +391,7 @@
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@@ -390,6 +390,7 @@
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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@ -24,7 +24,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
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#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
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#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
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#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
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@@ -476,6 +477,9 @@
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@@ -475,6 +476,9 @@
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#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
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#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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@ -7,7 +7,7 @@ Subject: [PATCH] ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -1226,6 +1226,10 @@
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@@ -1231,6 +1231,10 @@
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#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
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#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
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#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
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@ -16,7 +16,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -1246,7 +1246,12 @@
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@@ -1251,7 +1251,12 @@
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*/
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#define QCA955X_GMAC_REG_ETH_CFG 0x00
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@ -29,7 +29,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
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#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
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@@ -1268,9 +1273,58 @@
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@@ -1273,9 +1278,58 @@
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#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
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#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
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@ -21,7 +21,7 @@ Submitted-by: David Bauer <mail@david-bauer.net>
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -1376,5 +1376,6 @@
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@@ -1380,5 +1380,6 @@
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#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
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#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
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