mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
c60dd7bef9
The patches in the ath79 target have not been sorted for a long time and they are very chaotic now. This patch sorts them again according to the OpenWrt naming rules[1], so that we can better manage them. [1] https://openwrt.org/docs/guide-developer/toolchain/use-patches-with-buildsystem#naming_patches Signed-off-by: Shiji Yang <yangshiji66@qq.com>
31 lines
1.2 KiB
Diff
31 lines
1.2 KiB
Diff
From: David Bauer <mail@david-bauer.net>
|
|
Subject: [PATCH] ath79: force SGMII SerDes mode to MAC operation
|
|
|
|
The mode on the SGMII SerDes on the QCA9563 is 1000 Base-X by default.
|
|
This only allows for 1000 Mbit/s links, however when used with an SGMII
|
|
PHY in 100 Mbit/s link mode, the link remains dead.
|
|
|
|
This strictly has nothing to do with the SerDes calibration, however it
|
|
is done at the same point in the QCA reference U-Boot which is the
|
|
blueprint for everything happening here. As the current state is more or
|
|
less a hack, this should be fine.
|
|
|
|
This fixes the issues outlined above on a TP-Link EAP-225 Outdoor.
|
|
|
|
Reported-by: Tom Herbers <freifunk@tomherbers.de>
|
|
Tested-by: Tom Herbers <freifunk@tomherbers.de>
|
|
Submitted-by: David Bauer <mail@david-bauer.net>
|
|
---
|
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
|
|
1 files changed, 1 insertion(+)
|
|
|
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
@@ -1380,5 +1380,6 @@
|
|
|
|
#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
|
|
#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
|
|
+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC 0x2
|
|
|
|
#endif /* __ASM_MACH_AR71XX_REGS_H */
|