mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 22:23:27 +00:00
cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From b3841e7de0be51ddb4e0d17ab0561a12c6db2753 Mon Sep 17 00:00:00 2001
|
|
From: Alex Marginean <alexandru.marginean@nxp.com>
|
|
Date: Wed, 8 Jan 2020 12:34:33 +0200
|
|
Subject: [PATCH] drivers: net: dsa: felix: Allow PHY to AN 10/100/1000 with
|
|
2500 serdes link
|
|
|
|
If the serdes link is set to 2500 using interfce type 2500base-X, lower
|
|
link speeds over on the line side should still be supported.
|
|
Rate adaptation is done out of band, in our case using AQR PHYs this is
|
|
done using flow control.
|
|
|
|
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
|
---
|
|
drivers/net/dsa/ocelot/felix.c | 9 ++++-----
|
|
1 file changed, 4 insertions(+), 5 deletions(-)
|
|
|
|
--- a/drivers/net/dsa/ocelot/felix.c
|
|
+++ b/drivers/net/dsa/ocelot/felix.c
|
|
@@ -218,11 +218,10 @@ static void felix_phylink_validate(struc
|
|
phylink_set(mask, Autoneg);
|
|
phylink_set(mask, Pause);
|
|
phylink_set(mask, Asym_Pause);
|
|
- if (state->interface != PHY_INTERFACE_MODE_2500BASEX) {
|
|
- phylink_set(mask, 10baseT_Full);
|
|
- phylink_set(mask, 100baseT_Full);
|
|
- phylink_set(mask, 1000baseT_Full);
|
|
- }
|
|
+ phylink_set(mask, 10baseT_Full);
|
|
+ phylink_set(mask, 100baseT_Full);
|
|
+ phylink_set(mask, 1000baseT_Full);
|
|
+
|
|
/* The internal ports that run at 2.5G are overclocked GMII */
|
|
if (state->interface == PHY_INTERFACE_MODE_GMII ||
|
|
state->interface == PHY_INTERFACE_MODE_2500BASEX ||
|