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b40e6bc55f
In ath79, for several SoCs the console bootargs are defined to the
very same value in every device's DTS. Consolidate these definitions
in the SoC dtsi files and drop further redundant definitions elsewhere.
The only device without any bootargs set has been OpenMesh OM5P-AC V2.
This will now inherit the setting from qca955x.dtsi
While this is a cosmetic change, backporting it to 19.07 will be a
major help for anyone doing backports of device support. Without it,
every backporter would have to remember to manually add the chosen node
to the device's DTS.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 635f111148
)
238 lines
3.8 KiB
Plaintext
238 lines
3.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "ar7100.dtsi"
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/ {
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compatible = "dlink,dir-825-b1", "qca,ar7161";
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model = "D-Link DIR825B1";
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aliases {
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led-boot = &orange_power;
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led-failsafe = &orange_power;
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led-running = &blue_power;
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led-upgrade = &orange_power;
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};
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extosc: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "ref";
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clock-frequency = <40000000>;
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};
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leds {
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compatible = "gpio-leds";
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blue_usb {
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label = "d-link:blue:usb";
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gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
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trigger-sources = <&usb_ochi_port>, <&usb_echi_port>;
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linux,default-trigger = "usbport";
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};
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orange_power: orange_power {
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label = "d-link:orange:power";
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gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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blue_power: blue_power {
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label = "d-link:blue:power";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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};
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blue_wps {
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label = "d-link:blue:wps";
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gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
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};
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orange_planet {
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label = "d-link:orange:planet";
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gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
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};
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blue_planet {
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label = "d-link:blue:planet";
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gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
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};
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};
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ath9k-leds {
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compatible = "gpio-leds";
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wlan2g {
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label = "d-link:blue:wlan2g";
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gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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wlan5g {
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label = "d-link:blue:wlan5g";
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gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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rtl8366s {
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compatible = "realtek,rtl8366s";
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gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
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gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
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realtek,initvals = <0x06 0x0108>;
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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phy-mask = <0x10>;
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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};
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};
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};
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&usb1 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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usb_ochi_port: port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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};
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};
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&usb2 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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usb_echi_port: port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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};
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};
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&usb_phy {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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ath9k0: wifi@0,11 {
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compatible = "pci168c,0029";
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reg = <0x8800 0 0 0 0>;
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qca,no-eeprom;
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#gpio-cells = <2>;
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gpio-controller;
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};
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ath9k1: wifi@0,12 {
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compatible = "pci168c,0029";
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reg = <0x9000 0 0 0 0>;
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qca,no-eeprom;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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&uart {
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status = "okay";
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};
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&pll {
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clocks = <&extosc>;
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};
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&spi {
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status = "okay";
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num-cs = <1>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x000000 0x040000>;
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read-only;
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};
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partition@40000 {
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label = "config";
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reg = <0x040000 0x010000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x050000 0x610000>;
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};
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caldata: partition@60000 {
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label = "caldata";
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reg = <0x660000 0x010000>;
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read-only;
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};
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partition@670000 {
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label = "unknown";
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reg = <0x670000 0x190000>;
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read-only;
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};
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};
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};
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};
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ð0 {
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status = "okay";
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pll-data = <0x11110000 0x00001099 0x00991099>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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ð1 {
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status = "okay";
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pll-data = <0x11110000 0x00001099 0x00991099>;
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phy-handle = <&phy4>;
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};
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