mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
95 lines
2.7 KiB
Diff
95 lines
2.7 KiB
Diff
diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 2020-04-21 14:33:05.702816632 +0800
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c 2020-04-21 14:33:19.590328084 +0800
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@@ -2191,6 +2191,31 @@
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return 0;
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}
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+static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
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+{
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+ int i;
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+
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
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+ return;
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+
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+ for (i = 0; i < MTK_MAC_COUNT; i++) {
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+ u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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+
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+ /* default setup the forward port to send frame to PDMA */
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+ val &= ~0xffff;
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+
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+ /* Enable RX checksum */
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+ val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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+
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+ val |= config;
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+
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+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
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+ }
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+ /* Reset and enable PSE */
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+ mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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+ mtk_w32(eth, 0, MTK_RST_GL);
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+}
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+
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static int mtk_open(struct net_device *dev)
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{
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struct mtk_mac *mac = netdev_priv(dev);
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@@ -2211,6 +2236,8 @@
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if (err)
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return err;
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+ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
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+
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napi_enable(ð->tx_napi);
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napi_enable(ð->rx_napi);
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mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
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@@ -2266,6 +2293,8 @@
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if (!refcount_dec_and_test(ð->dma_refcnt))
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return 0;
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+ mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
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+
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mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
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mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
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napi_disable(ð->tx_napi);
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@@ -2392,8 +2421,6 @@
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mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
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mtk_tx_irq_disable(eth, ~0);
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mtk_rx_irq_disable(eth, ~0);
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- mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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- mtk_w32(eth, 0, MTK_RST_GL);
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/* FE int grouping */
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mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
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@@ -2402,19 +2429,6 @@
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mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
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mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
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- for (i = 0; i < MTK_MAC_COUNT; i++) {
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- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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-
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- /* setup the forward port to send frame to PDMA */
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- val &= ~0xffff;
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-
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- /* Enable RX checksum */
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- val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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-
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- /* setup the mac dma */
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- mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
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- }
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-
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return 0;
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err_disable_pm:
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diff -urN a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h 2020-04-21 14:33:10.702640743 +0800
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h 2020-04-21 14:33:24.902141220 +0800
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@@ -84,6 +84,8 @@
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#define MTK_GDMA_ICS_EN BIT(22)
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#define MTK_GDMA_TCS_EN BIT(21)
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#define MTK_GDMA_UCS_EN BIT(20)
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+#define MTK_GDMA_TO_PDMA 0x0
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+#define MTK_GDMA_DROP_ALL 0x7777
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/* Unicast Filter MAC Address Register - Low */
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#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
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