mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
9703a2adcc
Refresh all patches on top of kernel 5.10.138. The following patches were applied upstream: bcm27xx/patches-5.10/950-0311-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx/patches-5.10/950-0317-vc4_hdmi-Remove-firmware-logic-for-MAI-threshold-set.patch bcm27xx/patches-5.10/950-0346-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx/patches-5.10/950-0354-drm-vc4-Add-the-2711-HVS-as-a-suitable-DMA-node.patch bcm27xx/patches-5.10/950-0413-drm-vc4-hdmi-Don-t-access-the-connector-state-in-res.patch bcm27xx/patches-5.10/950-0505-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx/patches-5.10/950-0512-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx/patches-5.10/950-0560-drm-vc4-drv-Remove-the-DSI-pointer-in-vc4_drv.patch bcm27xx/patches-5.10/950-0561-drm-vc4-dsi-Use-snprintf-for-the-PHY-clocks-instead-.patch bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx/patches-5.10/950-0566-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx/patches-5.10/950-0567-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx/patches-5.10/950-0568-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx/patches-5.10/950-0695-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch Upstream sets the pixel clock to 340MHz now, do not set it to 600MHz any more. bcm27xx/patches-5.10/950-0576-drm-vc4-hdmi-Raise-the-maximum-clock-rate.patch Fixes:89956c6532("kernel: bump 5.10 to 5.10.138") Fixes:4209c33ae2("kernel: bump 5.10 to 5.10.137") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
63 lines
2.1 KiB
Diff
63 lines
2.1 KiB
Diff
From 4ec54ed688271966193b572ba5b150c6a4d270fc Mon Sep 17 00:00:00 2001
|
|
From: Tim Gover <tim.gover@raspberrypi.com>
|
|
Date: Thu, 24 Jun 2021 17:58:05 +0100
|
|
Subject: [PATCH] drm: vc4: Fix pixel-wrap issue with DVP teardown
|
|
|
|
Adjust the DVP enable/disable sequence to avoid a pixel getting stuck
|
|
in an internal, non resettable FIFO within PixelValve when changing
|
|
HDMI resolution.
|
|
|
|
The blank pixels features of the DVP can prevent signals back to
|
|
pixelvalve causing it to not clear the FIFO. Adjust the ordering
|
|
and timing of operations to ensure the clear signal makes it through to
|
|
pixelvalve.
|
|
|
|
Signed-off-by: Tim Gover <tim.gover@raspberrypi.com>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_hdmi.c | 15 ++++++++-------
|
|
1 file changed, 8 insertions(+), 7 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
@@ -613,12 +613,12 @@ static void vc4_hdmi_encoder_post_crtc_d
|
|
|
|
HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
|
|
|
|
- HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
|
|
- VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
|
|
+ HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
|
|
|
|
- HDMI_WRITE(HDMI_VID_CTL,
|
|
- HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
|
|
+ mdelay(1);
|
|
|
|
+ HDMI_WRITE(HDMI_VID_CTL,
|
|
+ HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
|
|
vc4_hdmi_disable_scrambling(encoder);
|
|
}
|
|
|
|
@@ -628,12 +628,12 @@ static void vc4_hdmi_encoder_post_crtc_p
|
|
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
|
|
int ret;
|
|
|
|
+ HDMI_WRITE(HDMI_VID_CTL,
|
|
+ HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
|
|
+
|
|
if (vc4_hdmi->variant->phy_disable)
|
|
vc4_hdmi->variant->phy_disable(vc4_hdmi);
|
|
|
|
- HDMI_WRITE(HDMI_VID_CTL,
|
|
- HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
|
|
-
|
|
clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
|
|
if (vc4_hdmi->bvb_req)
|
|
clk_request_done(vc4_hdmi->bvb_req);
|
|
@@ -1013,6 +1013,7 @@ static void vc4_hdmi_encoder_post_crtc_e
|
|
|
|
HDMI_WRITE(HDMI_VID_CTL,
|
|
VC4_HD_VID_CTL_ENABLE |
|
|
+ VC4_HD_VID_CTL_CLRRGB |
|
|
VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
|
|
VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
|
|
(vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
|