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9703a2adcc
Refresh all patches on top of kernel 5.10.138. The following patches were applied upstream: bcm27xx/patches-5.10/950-0311-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx/patches-5.10/950-0317-vc4_hdmi-Remove-firmware-logic-for-MAI-threshold-set.patch bcm27xx/patches-5.10/950-0346-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx/patches-5.10/950-0354-drm-vc4-Add-the-2711-HVS-as-a-suitable-DMA-node.patch bcm27xx/patches-5.10/950-0413-drm-vc4-hdmi-Don-t-access-the-connector-state-in-res.patch bcm27xx/patches-5.10/950-0505-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx/patches-5.10/950-0512-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx/patches-5.10/950-0560-drm-vc4-drv-Remove-the-DSI-pointer-in-vc4_drv.patch bcm27xx/patches-5.10/950-0561-drm-vc4-dsi-Use-snprintf-for-the-PHY-clocks-instead-.patch bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx/patches-5.10/950-0566-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx/patches-5.10/950-0567-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx/patches-5.10/950-0568-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx/patches-5.10/950-0695-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch Upstream sets the pixel clock to 340MHz now, do not set it to 600MHz any more. bcm27xx/patches-5.10/950-0576-drm-vc4-hdmi-Raise-the-maximum-clock-rate.patch Fixes:89956c6532
("kernel: bump 5.10 to 5.10.138") Fixes:4209c33ae2
("kernel: bump 5.10 to 5.10.137") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
92 lines
3.1 KiB
Diff
92 lines
3.1 KiB
Diff
From c20cb28d802aa148cfa90c0682323e9d52dc0466 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Fri, 7 May 2021 15:28:21 +0200
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Subject: [PATCH] drm/vc4: hdmi: Add a workqueue to set scrambling
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It looks like some displays (like the LG 27UL850-W) don't enable the
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scrambling when the HDMI driver enables it. However, if we set later the
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scrambler enable bit, the display will work as expected.
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Let's create delayed work queue to periodically look at the display
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scrambling status, and if it's not set yet try to enable it again.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 25 +++++++++++++++++++++++++
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drivers/gpu/drm/vc4/vc4_hdmi.h | 2 ++
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2 files changed, 27 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -540,6 +540,8 @@ static bool vc4_hdmi_supports_scrambling
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return true;
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}
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+#define SCRAMBLING_POLLING_DELAY_MS 1000
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+
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static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
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{
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struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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@@ -556,6 +558,9 @@ static void vc4_hdmi_enable_scrambling(s
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HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
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VC5_HDMI_SCRAMBLER_CTL_ENABLE);
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+
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+ queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
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+ msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
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}
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static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
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@@ -574,6 +579,9 @@ static void vc4_hdmi_disable_scrambling(
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if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
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return;
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+ if (delayed_work_pending(&vc4_hdmi->scrambling_work))
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+ cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
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+
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HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
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~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
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@@ -581,6 +589,22 @@ static void vc4_hdmi_disable_scrambling(
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drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
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}
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+static void vc4_hdmi_scrambling_wq(struct work_struct *work)
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+{
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+ struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
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+ struct vc4_hdmi,
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+ scrambling_work);
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+
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+ if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
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+ return;
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+
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+ drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
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+ drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
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+
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+ queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
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+ msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
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+}
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+
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static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
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struct drm_atomic_state *state)
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{
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@@ -2275,6 +2299,7 @@ static int vc4_hdmi_bind(struct device *
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vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
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if (!vc4_hdmi)
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return -ENOMEM;
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+ INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
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dev_set_drvdata(dev, vc4_hdmi);
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encoder = &vc4_hdmi->encoder.base.base;
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -131,6 +131,8 @@ struct vc4_hdmi {
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struct vc4_hdmi_encoder encoder;
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struct drm_connector connector;
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+ struct delayed_work scrambling_work;
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+
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struct i2c_adapter *ddc;
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void __iomem *hdmicore_regs;
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void __iomem *hd_regs;
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