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Refresh all patches on top of kernel 5.10.138. The following patches were applied upstream: bcm27xx/patches-5.10/950-0311-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx/patches-5.10/950-0317-vc4_hdmi-Remove-firmware-logic-for-MAI-threshold-set.patch bcm27xx/patches-5.10/950-0346-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx/patches-5.10/950-0354-drm-vc4-Add-the-2711-HVS-as-a-suitable-DMA-node.patch bcm27xx/patches-5.10/950-0413-drm-vc4-hdmi-Don-t-access-the-connector-state-in-res.patch bcm27xx/patches-5.10/950-0505-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx/patches-5.10/950-0512-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx/patches-5.10/950-0560-drm-vc4-drv-Remove-the-DSI-pointer-in-vc4_drv.patch bcm27xx/patches-5.10/950-0561-drm-vc4-dsi-Use-snprintf-for-the-PHY-clocks-instead-.patch bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx/patches-5.10/950-0566-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx/patches-5.10/950-0567-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx/patches-5.10/950-0568-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx/patches-5.10/950-0695-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch Upstream sets the pixel clock to 340MHz now, do not set it to 600MHz any more. bcm27xx/patches-5.10/950-0576-drm-vc4-hdmi-Raise-the-maximum-clock-rate.patch Fixes:89956c6532("kernel: bump 5.10 to 5.10.138") Fixes:4209c33ae2("kernel: bump 5.10 to 5.10.137") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
61 lines
2.0 KiB
Diff
61 lines
2.0 KiB
Diff
From b4627f9f36d8af7cb7bf24d8c1daee8b48f12299 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Mon, 11 Jan 2021 15:23:02 +0100
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Subject: [PATCH] drm/vc4: hdmi: Introduce a CEC clock
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While the BCM2835 had the CEC clock derived from the HSM clock, the
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BCM2711 has a dedicated parent clock for it.
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Let's introduce a separate clock for it so that we can handle both
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cases.
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Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 9 ++++++++-
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drivers/gpu/drm/vc4/vc4_hdmi.h | 1 +
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2 files changed, 9 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -153,7 +153,7 @@ static void vc4_hdmi_cec_update_clk_div(
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* Set the clock divider: the hsm_clock rate and this divider
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* setting will give a 40 kHz CEC clock.
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*/
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- clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;
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+ clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
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value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
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HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
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}
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@@ -1869,6 +1869,7 @@ static int vc4_hdmi_init_resources(struc
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return PTR_ERR(vc4_hdmi->hsm_clock);
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}
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vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
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+ vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
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return 0;
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}
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@@ -1963,6 +1964,12 @@ static int vc5_hdmi_init_resources(struc
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return PTR_ERR(vc4_hdmi->audio_clock);
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}
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+ vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
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+ if (IS_ERR(vc4_hdmi->cec_clock)) {
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+ DRM_ERROR("Failed to get CEC clock\n");
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+ return PTR_ERR(vc4_hdmi->cec_clock);
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+ }
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+
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vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
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if (IS_ERR(vc4_hdmi->reset)) {
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DRM_ERROR("Failed to get HDMI reset line\n");
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -154,6 +154,7 @@ struct vc4_hdmi {
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bool cec_tx_ok;
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bool cec_irq_was_rx;
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+ struct clk *cec_clock;
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struct clk *pixel_clock;
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struct clk *hsm_clock;
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struct clk *audio_clock;
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