mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
6a0a6c45ed
Backport upstreamed dts updates for rk3588. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
54 lines
2.0 KiB
Diff
54 lines
2.0 KiB
Diff
From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001
|
|
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
|
Date: Tue, 9 Apr 2024 00:50:32 +0200
|
|
Subject: [PATCH] arm64: dts: rockchip: reorder usb2phy properties for rk3588
|
|
|
|
Reorder common DT properties alphabetically for usb2phy, according
|
|
to latest DT style rules.
|
|
|
|
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
|
Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com
|
|
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++--------
|
|
1 file changed, 8 insertions(+), 8 deletions(-)
|
|
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
|
@@ -602,13 +602,13 @@
|
|
u2phy2: usb2phy@8000 {
|
|
compatible = "rockchip,rk3588-usb2phy";
|
|
reg = <0x8000 0x10>;
|
|
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
|
- reset-names = "phy", "apb";
|
|
+ #clock-cells = <0>;
|
|
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
clock-names = "phyclk";
|
|
clock-output-names = "usb480m_phy2";
|
|
- #clock-cells = <0>;
|
|
+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
|
+ reset-names = "phy", "apb";
|
|
status = "disabled";
|
|
|
|
u2phy2_host: host-port {
|
|
@@ -627,13 +627,13 @@
|
|
u2phy3: usb2phy@c000 {
|
|
compatible = "rockchip,rk3588-usb2phy";
|
|
reg = <0xc000 0x10>;
|
|
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
|
- reset-names = "phy", "apb";
|
|
+ #clock-cells = <0>;
|
|
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
clock-names = "phyclk";
|
|
clock-output-names = "usb480m_phy3";
|
|
- #clock-cells = <0>;
|
|
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
|
+ reset-names = "phy", "apb";
|
|
status = "disabled";
|
|
|
|
u2phy3_host: host-port {
|