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dca5bf6d53
Add patch headers and description for pending patch. Add version tag to patch already merged upstream. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
104 lines
3.4 KiB
Diff
104 lines
3.4 KiB
Diff
From patchwork Wed Oct 19 14:37:35 2022
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
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X-Patchwork-Id: 13011901
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Date: Wed, 19 Oct 2022 15:37:35 +0100
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From: Daniel Golle <daniel@makrotopia.org>
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To: Jonathan Cameron <jic23@kernel.org>,
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Lars-Peter Clausen <lars@metafoo.de>,
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Matthias Brugger <matthias.bgg@gmail.com>,
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linux-iio@vger.kernel.org
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Cc: David Bauer <mail@david-bauer.net>,
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Gwendal Grignou <gwendal@chromium.org>,
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AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
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linux-arm-kernel@lists.infradead.org,
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linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
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Subject: [PATCH 1/2] iio: adc: mt6577_auxadc: add optional 32k clock
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Message-ID:
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<f98ed7f3fc15a0614443a57427d46ce17ec2e0cc.1666190235.git.daniel@makrotopia.org>
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MIME-Version: 1.0
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Content-Disposition: inline
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X-BeenThere: linux-mediatek@lists.infradead.org
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X-Mailman-Version: 2.1.34
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Precedence: list
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List-Id: <linux-mediatek.lists.infradead.org>
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MediaTek MT7986 and MT7981 require an additional clock to be brought up
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for AUXADC. Add support for that in the driver, similar to how it's
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done in MediaTek's SDK[1].
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[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/target/linux/mediatek/patches-5.4/500-auxadc-add-auxadc-32k-clk.patch
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/iio/adc/mt6577_auxadc.c | 22 ++++++++++++++++++++++
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1 file changed, 22 insertions(+)
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--- a/drivers/iio/adc/mt6577_auxadc.c
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+++ b/drivers/iio/adc/mt6577_auxadc.c
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@@ -42,6 +42,7 @@ struct mtk_auxadc_compatible {
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struct mt6577_auxadc_device {
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void __iomem *reg_base;
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struct clk *adc_clk;
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+ struct clk *adc_32k_clk;
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struct mutex lock;
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const struct mtk_auxadc_compatible *dev_comp;
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};
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@@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_
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return ret;
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}
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+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
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+ if (ret) {
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+ pr_err("failed to enable auxadc clock\n");
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+ return ret;
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+ }
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+
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
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MT6577_AUXADC_PDN_EN, 0);
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mdelay(MT6577_AUXADC_POWER_READY_MS);
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@@ -236,6 +243,8 @@ static int __maybe_unused mt6577_auxadc_
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
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0, MT6577_AUXADC_PDN_EN);
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+
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+ clk_disable_unprepare(adc_dev->adc_32k_clk);
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clk_disable_unprepare(adc_dev->adc_clk);
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return 0;
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@@ -277,6 +286,17 @@ static int mt6577_auxadc_probe(struct pl
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return ret;
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}
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+ adc_dev->adc_32k_clk = devm_clk_get_optional(&pdev->dev, "32k");
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+ if (IS_ERR(adc_dev->adc_32k_clk)) {
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+ dev_err(&pdev->dev, "failed to get auxadc 32k clock\n");
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+ return PTR_ERR(adc_dev->adc_32k_clk);
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+ }
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+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
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+ if (ret) {
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+ dev_err(&pdev->dev, "failed to enable auxadc 32k clock\n");
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+ return ret;
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+ }
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+
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adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
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if (!adc_clk_rate) {
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ret = -EINVAL;
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@@ -306,6 +326,7 @@ err_power_off:
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
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0, MT6577_AUXADC_PDN_EN);
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err_disable_clk:
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+ clk_disable_unprepare(adc_dev->adc_32k_clk);
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clk_disable_unprepare(adc_dev->adc_clk);
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return ret;
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}
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@@ -320,6 +341,7 @@ static int mt6577_auxadc_remove(struct p
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
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0, MT6577_AUXADC_PDN_EN);
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+ clk_disable_unprepare(adc_dev->adc_32k_clk);
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clk_disable_unprepare(adc_dev->adc_clk);
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return 0;
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