From patchwork Wed Oct 19 14:37:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 13011901 Date: Wed, 19 Oct 2022 15:37:35 +0100 From: Daniel Golle To: Jonathan Cameron , Lars-Peter Clausen , Matthias Brugger , linux-iio@vger.kernel.org Cc: David Bauer , Gwendal Grignou , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] iio: adc: mt6577_auxadc: add optional 32k clock Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: MediaTek MT7986 and MT7981 require an additional clock to be brought up for AUXADC. Add support for that in the driver, similar to how it's done in MediaTek's SDK[1]. [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/target/linux/mediatek/patches-5.4/500-auxadc-add-auxadc-32k-clk.patch Signed-off-by: Daniel Golle --- drivers/iio/adc/mt6577_auxadc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) --- a/drivers/iio/adc/mt6577_auxadc.c +++ b/drivers/iio/adc/mt6577_auxadc.c @@ -42,6 +42,7 @@ struct mtk_auxadc_compatible { struct mt6577_auxadc_device { void __iomem *reg_base; struct clk *adc_clk; + struct clk *adc_32k_clk; struct mutex lock; const struct mtk_auxadc_compatible *dev_comp; }; @@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_ return ret; } + ret = clk_prepare_enable(adc_dev->adc_32k_clk); + if (ret) { + pr_err("failed to enable auxadc clock\n"); + return ret; + } + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, MT6577_AUXADC_PDN_EN, 0); mdelay(MT6577_AUXADC_POWER_READY_MS); @@ -236,6 +243,8 @@ static int __maybe_unused mt6577_auxadc_ mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 0, MT6577_AUXADC_PDN_EN); + + clk_disable_unprepare(adc_dev->adc_32k_clk); clk_disable_unprepare(adc_dev->adc_clk); return 0; @@ -277,6 +286,17 @@ static int mt6577_auxadc_probe(struct pl return ret; } + adc_dev->adc_32k_clk = devm_clk_get_optional(&pdev->dev, "32k"); + if (IS_ERR(adc_dev->adc_32k_clk)) { + dev_err(&pdev->dev, "failed to get auxadc 32k clock\n"); + return PTR_ERR(adc_dev->adc_32k_clk); + } + ret = clk_prepare_enable(adc_dev->adc_32k_clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable auxadc 32k clock\n"); + return ret; + } + adc_clk_rate = clk_get_rate(adc_dev->adc_clk); if (!adc_clk_rate) { ret = -EINVAL; @@ -306,6 +326,7 @@ err_power_off: mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 0, MT6577_AUXADC_PDN_EN); err_disable_clk: + clk_disable_unprepare(adc_dev->adc_32k_clk); clk_disable_unprepare(adc_dev->adc_clk); return ret; } @@ -320,6 +341,7 @@ static int mt6577_auxadc_remove(struct p mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, 0, MT6577_AUXADC_PDN_EN); + clk_disable_unprepare(adc_dev->adc_32k_clk); clk_disable_unprepare(adc_dev->adc_clk); return 0;