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Armada 370 processors have only 16 double-precision registers. The change introduced by8dcc108760("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for mvebu cortexa9 subtarget to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes:8dcc108760("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl> (cherry picked from commit2d61f8821c)
15 lines
297 B
Makefile
15 lines
297 B
Makefile
#
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# Copyright (C) 2017 Hauke Mehrtens
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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ARCH:=arm
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BOARDNAME:=Marvell Armada 37x/38x/XP
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CPU_TYPE:=cortex-a9
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CPU_SUBTYPE:=vfpv3-d16
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KERNELNAME:=zImage dtbs
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