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58f4667a37
New stm32 target introduces support for stm32mp1 based devices.
For now it includes an initial support of the STM32MP135F-DK device.
The specifications bellow only list supported features.
Specifications
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SOC: STM32MP135FAF7
RAM: 512 MiB
Storage: SD Card
Ethernet: 2x 100 Mbps
Wireless: 2.4GHz Cypress CYW43455 (802.11b/g/n)
LEDs: Heartbeat (Blue)
Buttons: 1x Reset, 1x User (USER2)
USB: 4x 2.0 Type-A
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/16716
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 851e7f77e4)
Link: https://github.com/openwrt/openwrt/pull/17097
Signed-off-by: Petr Štetiar <ynezz@true.cz>
127 lines
4.4 KiB
Diff
127 lines
4.4 KiB
Diff
From b1468a44e0c0f43a06e027efeff4183b3aee0cf7 Mon Sep 17 00:00:00 2001
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From: Christophe Roullier <christophe.roullier@foss.st.com>
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Date: Mon, 10 Jun 2024 10:03:08 +0200
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Subject: [PATCH 3/5] ARM: dts: stm32: add ethernet1/2 RMII pins for
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STM32MP13F-DK board
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Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board.
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ethernet1: RMII with crystal.
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ethernet2: RMII without crystal.
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Add analog gpio pin configuration ("sleep") to manage power mode on
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stm32mp13.
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Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
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Reviewed-by: Marek Vasut <marex@denx.de>
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Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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---
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arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 98 +++++++++++++++++++++
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1 file changed, 98 insertions(+)
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--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
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+++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
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@@ -13,6 +13,104 @@
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};
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};
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+ eth1_rgmii_pins_a: eth1-rgmii-0 {
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+ pins1 {
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+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
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+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
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+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
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+ <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
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+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
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+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
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+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
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+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
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+ bias-disable;
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+ drive-push-pull;
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+ slew-rate = <2>;
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+ };
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+
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+ pins2 {
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+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
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+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
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+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
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+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
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+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
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+ <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
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+ bias-disable;
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+ };
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+
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+ };
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+
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+ eth1_rmii_pins_a: eth1-rmii-0 {
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+ pins1 {
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+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
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+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
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+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
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+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
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+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
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+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
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+ bias-disable;
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+ drive-push-pull;
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+ slew-rate = <1>;
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+ };
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+
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+ pins2 {
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+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
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+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
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+ <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
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+ bias-disable;
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+ };
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+
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+ };
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+
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+ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 {
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+ pins1 {
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+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
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+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
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+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
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+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
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+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
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+ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
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+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
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+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
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+ <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
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+ };
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+ };
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+
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+ eth2_rmii_pins_a: eth2-rmii-0 {
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+ pins1 {
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+ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
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+ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
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+ <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
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+ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
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+ <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
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+ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
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+ bias-disable;
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+ drive-push-pull;
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+ slew-rate = <1>;
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+ };
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+
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+ pins2 {
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+ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
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+ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
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+ <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
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+ bias-disable;
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+ };
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+ };
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+
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+ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 {
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+ pins1 {
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+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
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+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
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+ <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
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+ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
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+ <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
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+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
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+ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
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+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
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+ <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
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+ };
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+ };
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+
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i2c1_pins_a: i2c1-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
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