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6a0a6c45ed
Backport upstreamed dts updates for rk3588. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
176 lines
5.3 KiB
Diff
176 lines
5.3 KiB
Diff
From e18e5e8188f2671abf63abe7db5f21555705130f Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Tue, 9 Apr 2024 00:50:33 +0200
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Subject: [PATCH] arm64: dts: rockchip: add USBDP phys on rk3588
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Add both USB3-DisplayPort PHYs to RK3588 SoC DT.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588.dtsi | 52 +++++++++++++++++++
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++
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2 files changed, 115 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -17,6 +17,36 @@
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reg = <0x0 0xfd5c0000 0x0 0x100>;
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};
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+ usbdpphy1_grf: syscon@fd5cc000 {
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+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
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+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
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+ };
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+
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+ usb2phy1_grf: syscon@fd5d4000 {
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+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
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+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ u2phy1: usb2phy@4000 {
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+ compatible = "rockchip,rk3588-usb2phy";
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+ reg = <0x4000 0x10>;
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+ #clock-cells = <0>;
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+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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+ clock-names = "phyclk";
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+ clock-output-names = "usb480m_phy1";
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+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
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+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
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+ reset-names = "phy", "apb";
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+ status = "disabled";
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+
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+ u2phy1_otg: otg-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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i2s8_8ch: i2s@fddc8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc8000 0x0 0x1000>;
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@@ -310,6 +340,28 @@
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};
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};
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+ usbdp_phy1: phy@fed90000 {
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+ compatible = "rockchip,rk3588-usbdp-phy";
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+ reg = <0x0 0xfed90000 0x0 0x10000>;
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+ #phy-cells = <1>;
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+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
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+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
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+ <&cru PCLK_USBDPPHY1>,
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+ <&u2phy1>;
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+ clock-names = "refclk", "immortal", "pclk", "utmi";
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+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
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+ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
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+ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
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+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
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+ <&cru SRST_P_USBDPPHY1>;
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+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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+ rockchip,u2phy-grf = <&usb2phy1_grf>;
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+ rockchip,usb-grf = <&usb_grf>;
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+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
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+ rockchip,vo-grf = <&vo0_grf>;
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+ status = "disabled";
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+ };
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+
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combphy1_ps: phy@fee10000 {
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compatible = "rockchip,rk3588-naneng-combphy";
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reg = <0x0 0xfee10000 0x0 0x100>;
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -572,12 +572,23 @@
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reg = <0x0 0xfd5a4000 0x0 0x2000>;
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};
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+ vo0_grf: syscon@fd5a6000 {
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+ compatible = "rockchip,rk3588-vo-grf", "syscon";
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+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
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+ clocks = <&cru PCLK_VO0GRF>;
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+ };
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+
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vo1_grf: syscon@fd5a8000 {
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compatible = "rockchip,rk3588-vo-grf", "syscon";
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reg = <0x0 0xfd5a8000 0x0 0x100>;
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clocks = <&cru PCLK_VO1GRF>;
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};
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+ usb_grf: syscon@fd5ac000 {
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+ compatible = "rockchip,rk3588-usb-grf", "syscon";
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+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
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+ };
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+
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php_grf: syscon@fd5b0000 {
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compatible = "rockchip,rk3588-php-grf", "syscon";
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reg = <0x0 0xfd5b0000 0x0 0x1000>;
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@@ -593,6 +604,36 @@
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reg = <0x0 0xfd5c4000 0x0 0x100>;
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};
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+ usbdpphy0_grf: syscon@fd5c8000 {
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+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
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+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
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+ };
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+
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+ usb2phy0_grf: syscon@fd5d0000 {
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+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
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+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ u2phy0: usb2phy@0 {
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+ compatible = "rockchip,rk3588-usb2phy";
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+ reg = <0x0 0x10>;
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+ #clock-cells = <0>;
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+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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+ clock-names = "phyclk";
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+ clock-output-names = "usb480m_phy0";
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+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
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+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
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+ reset-names = "phy", "apb";
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+ status = "disabled";
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+
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+ u2phy0_otg: otg-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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usb2phy2_grf: syscon@fd5d8000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
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reg = <0x0 0xfd5d8000 0x0 0x4000>;
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@@ -2449,6 +2490,28 @@
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status = "disabled";
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};
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+ usbdp_phy0: phy@fed80000 {
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+ compatible = "rockchip,rk3588-usbdp-phy";
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+ reg = <0x0 0xfed80000 0x0 0x10000>;
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+ #phy-cells = <1>;
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+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
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+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
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+ <&cru PCLK_USBDPPHY0>,
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+ <&u2phy0>;
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+ clock-names = "refclk", "immortal", "pclk", "utmi";
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+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
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+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
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+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
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+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
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+ <&cru SRST_P_USBDPPHY0>;
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+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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+ rockchip,u2phy-grf = <&usb2phy0_grf>;
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+ rockchip,usb-grf = <&usb_grf>;
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+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
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+ rockchip,vo-grf = <&vo0_grf>;
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+ status = "disabled";
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+ };
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+
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combphy0_ps: phy@fee00000 {
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compatible = "rockchip,rk3588-naneng-combphy";
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reg = <0x0 0xfee00000 0x0 0x100>;
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