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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
115 lines
2.7 KiB
Diff
115 lines
2.7 KiB
Diff
From 3261cabf5607c9f434faa4930ab5c2b0150579c4 Mon Sep 17 00:00:00 2001
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From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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Date: Wed, 29 Nov 2017 06:23:14 +0530
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Subject: [PATCH] arm64: dts: ls1012a: Add LS1012A-2G5RDB board support
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LS1012A-2G5RDB is a different design from LS1012ARDB,
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but has some common SoC features. Key feature on this
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board is 2.5Gbps SGMII.
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Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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Signed-off-by: Li Yang <leoyang.li@nxp.com>
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---
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arch/arm64/boot/dts/freescale/Makefile | 1 +
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.../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 86 ++++++++++++++++++++++
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2 files changed, 87 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
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--- a/arch/arm64/boot/dts/freescale/Makefile
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+++ b/arch/arm64/boot/dts/freescale/Makefile
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@@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
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@@ -0,0 +1,86 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree file for NXP LS1012A 2G5RDB Board.
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+ *
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+ * Copyright 2017 NXP
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+ *
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+ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
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+ */
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+/dts-v1/;
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+
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+#include "fsl-ls1012a.dtsi"
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+
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+/ {
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+ model = "LS1012A 2G5RDB Board";
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+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
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+
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+ aliases {
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+ ethernet0 = &pfe_mac0;
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+ ethernet1 = &pfe_mac1;
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+ };
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+};
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+
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+&duart0 {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+};
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+
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+&qspi {
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+ num-cs = <2>;
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+ bus-num = <0>;
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+ status = "okay";
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+
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+ qflash0: s25fs512s@0 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ m25p,fast-read;
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+ reg = <0>;
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+ };
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+};
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+
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+&sata {
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+ status = "okay";
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+};
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+
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+&pfe {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethernet@0 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0>; /* GEM_ID */
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+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii-2500";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x1>; /* enabled/disabled */
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+ };
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+ };
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+
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+ ethernet@1 {
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+ compatible = "fsl,pfe-gemac-port";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>; /* GEM_ID */
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+ fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
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+ fsl,gemac-phy-id = < 0x2>; /* PHY_ID */
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+ fsl,mdio-mux-val = <0x0>;
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+ phy-mode = "sgmii-2500";
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+ fsl,pfe-phy-if-flags = <0x0>;
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+
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+ mdio@0 {
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+ reg = <0x0>; /* enabled/disabled */
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+ };
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+ };
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+};
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