Shiji Yang 8d4c22a956 ath79: add missing clock name strings in SoC dtsi ... For all SoC in the ath79 target, the PLL controller provides 3 main clocks "cpu", "ddr" and "ahb" through the input clock "ref". Signed-off-by: Shiji Yang <yangshiji66@qq.com>		2022-11-09 22:55:33 +01:00
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base-files/etc/hotplug.d/ieee80211	ath79: migrate Archer C5 5GHz radio device paths	2022-03-31 18:07:29 +02:00
dts	ath79: add missing clock name strings in SoC dtsi	2022-11-09 22:55:33 +01:00
files	ath79: increase max tx ring buffer for ag71xx	2022-10-06 16:45:43 +02:00
generic	ath79: add support to TrendNet TEW-673GRU	2022-11-06 00:51:58 +01:00
image	ath79: add support to TrendNet TEW-673GRU	2022-11-06 00:51:58 +01:00
mikrotik	ath79: move 5.15 testing kernel to common Makefile	2022-09-06 02:57:35 +02:00
nand	ath79: add support for Linksys EA4500 v3	2022-10-30 23:14:45 +01:00
patches-5.10	kernel: backport support for "linux,rootfs" in DT	2022-11-08 09:12:16 +01:00
patches-5.15	kernel: backport support for "linux,rootfs" in DT	2022-11-08 09:12:16 +01:00
tiny	ath79: add support for TP-Link TL-WR941ND v5	2022-09-11 22:00:22 +02:00
config-5.10	kernel: mtd: backport SafeLoader parser	2022-10-19 07:07:14 +02:00
config-5.15	kernel: mtd: backport SafeLoader parser	2022-10-19 07:07:14 +02:00
Makefile	ath79: switch to 5.15 as default kernel	2022-09-24 13:04:24 +02:00
modules.mk	ath79: add new OF only target for QCA MIPS silicon	2018-05-07 08:06:51 +02:00