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4108c0c1b6
- Mark patches as upstream - Backport more upstream changes - Handle conflicts and refresh patches Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
96 lines
3.2 KiB
Diff
96 lines
3.2 KiB
Diff
From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001
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From: Krishna Kurapati <quic_kriskura@quicinc.com>
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Date: Fri, 26 Jan 2024 00:29:18 +0530
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Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
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On several QUSB2 Targets, the hs_phy_irq mentioned is actually
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qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
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to qusb2_phy for such targets.
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In actuality, the hs_phy_irq is also present in these targets, but
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kept in for debug purposes in hw test environments. This is not
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triggered by default and its functionality is mutually exclusive
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to that of qusb2_phy interrupt.
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Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
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Add missing ss_phy_irq on some targets which allows for remote
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wakeup to work on a Super Speed link.
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Also modify order of interrupts in accordance to bindings update.
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Since driver looks up for interrupts by name and not by index, it
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is safe to modify order of these interrupts in the DT.
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Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
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Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
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arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++--
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arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++--
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arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++--
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arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++----
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arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++--
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arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++--
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8 files changed, 70 insertions(+), 14 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -430,6 +430,12 @@
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<&gcc GCC_USB1_MOCK_UTMI_CLK>;
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assigned-clock-rates = <133330000>,
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<24000000>;
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+
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+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pwr_event",
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+ "qusb2_phy";
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+
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resets = <&gcc GCC_USB1_BCR>;
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status = "disabled";
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@@ -628,6 +634,13 @@
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<133330000>,
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<24000000>;
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+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pwr_event",
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+ "qusb2_phy",
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+ "ss_phy_irq";
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+
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resets = <&gcc GCC_USB0_BCR>;
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status = "disabled";
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -611,6 +611,13 @@
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<133330000>,
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<19200000>;
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+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pwr_event",
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+ "qusb2_phy",
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+ "ss_phy_irq";
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+
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power-domains = <&gcc USB0_GDSC>;
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resets = <&gcc GCC_USB0_BCR>;
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@@ -653,6 +660,13 @@
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<133330000>,
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<19200000>;
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+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pwr_event",
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+ "qusb2_phy",
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+ "ss_phy_irq";
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+
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power-domains = <&gcc USB1_GDSC>;
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resets = <&gcc GCC_USB1_BCR>;
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