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qualcommax: backport more changes for ipq6018 and ipq8074

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- Mark patches as upstream
 - Backport more upstream changes
 - Handle conflicts and refresh patches

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
This commit is contained in:
Chukun Pan 2024-01-15 23:28:13 +08:00 committed by Robert Marko
parent bf304d10e9
commit 4108c0c1b6
48 changed files with 1810 additions and 126 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
target/linux/qualcommax/patches-6.1/0008-v6.2-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch Normal file
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@ -0,0 +1,28 @@
From 8857b0ab6a562c473c5bded0efda9390b82a84d4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 27 Sep 2022 22:12:17 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: fix NAND node name
Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
Fix it to match nand-controller.yaml requirements.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927201218.1264506-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -348,7 +348,7 @@
status = "disabled";
};
- qpic_nand: nand@79b0000 {
+ qpic_nand: nand-controller@79b0000 {
compatible = "qcom,ipq6018-nand";
reg = <0x0 0x079b0000 0x0 0x10000>;
#address-cells = <1>;

56
target/linux/qualcommax/patches-6.1/0018-v6.2-arm64-dts-qcom-ipq6018-align-TLMM-pin-configuration-.patch Normal file
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@ -0,0 +1,56 @@
From 20afb6751739264ea41993877de93923911dfdc3 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 6 Oct 2022 14:46:27 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: align TLMM pin configuration with
DT schema
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221006124659.217540-3-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++--
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -51,13 +51,13 @@
};
&tlmm {
- i2c_1_pins: i2c-1-pins {
+ i2c_1_pins: i2c-1-state {
pins = "gpio42", "gpio43";
function = "blsp2_i2c";
drive-strength = <8>;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -218,14 +218,14 @@
interrupt-controller;
#interrupt-cells = <2>;
- serial_3_pins: serial3-pinmux {
+ serial_3_pins: serial3-state {
pins = "gpio44", "gpio45";
function = "blsp2_uart";
drive-strength = <8>;
bias-pull-down;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",

26
target/linux/qualcommax/patches-6.1/0022-v6.4-arm64-dts-qcom-ipq8074-add-compatible-fallback-to.patch Normal file
View File

@ -0,0 +1,26 @@
From d93bd4630ce163f3761aedc0b342b072bee6db6b Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 22 Mar 2023 18:41:40 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: add compatible fallback to mailbox
IPQ8074 mailbox is compatible with IPQ6018.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-4-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -682,7 +682,8 @@
};
apcs_glb: mailbox@b111000 {
- compatible = "qcom,ipq8074-apcs-apps-global";
+ compatible = "qcom,ipq8074-apcs-apps-global",
+ "qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
clocks = <&a53pll>, <&xo>;
clock-names = "pll", "xo";

24
target/linux/qualcommax/patches-6.1/0023-v6.5-arm64-dts-qcom-ipq8074-add-critical-thermal-trips.patch
View File

@ -17,7 +17,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -898,6 +898,14 @@
@@ -899,6 +899,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
@ -32,7 +32,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
nss0-thermal {
@@ -905,6 +913,14 @@
@@ -906,6 +914,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@ -47,7 +47,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
nss1-thermal {
@@ -912,6 +928,14 @@
@@ -913,6 +929,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
@ -62,7 +62,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
wcss-phya0-thermal {
@@ -919,6 +943,14 @@
@@ -920,6 +944,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
@ -77,7 +77,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
wcss-phya1-thermal {
@@ -926,6 +958,14 @@
@@ -927,6 +959,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
@ -92,7 +92,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
cpu0_thermal: cpu0-thermal {
@@ -933,6 +973,14 @@
@@ -934,6 +974,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
@ -107,7 +107,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
cpu1_thermal: cpu1-thermal {
@@ -940,6 +988,14 @@
@@ -941,6 +989,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 10>;
@ -122,7 +122,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
cpu2_thermal: cpu2-thermal {
@@ -947,6 +1003,14 @@
@@ -948,6 +1004,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 11>;
@ -137,7 +137,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
cpu3_thermal: cpu3-thermal {
@@ -954,6 +1018,14 @@
@@ -955,6 +1019,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 12>;
@ -152,7 +152,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
cluster_thermal: cluster-thermal {
@@ -961,6 +1033,14 @@
@@ -962,6 +1034,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 13>;
@ -167,7 +167,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
wcss-phyb0-thermal {
@@ -968,6 +1048,14 @@
@@ -969,6 +1049,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 14>;
@ -182,7 +182,7 @@ Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
};
wcss-phyb1-thermal {
@@ -975,6 +1063,14 @@
@@ -976,6 +1064,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 15>;

26
target/linux/qualcommax/patches-6.1/0038-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch → target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++++++++++
drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++
2 files changed, 59 insertions(+)
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
@ -31,20 +31,20 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+ { .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
{ .compatible = "qcom,ipq8074", },
{ .compatible = "qcom,apq8064", },
{ .compatible = "qcom,msm8974", },
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -36,6 +36,8 @@ enum ipq8074_versions {
IPQ8074_ACORN_VERSION,
};
@@ -31,6 +31,8 @@
#include <dt-bindings/arm/qcom,ids.h>
+#define IPQ6000_VERSION BIT(2)
+
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -209,6 +211,57 @@ len_error:
@@ -204,6 +206,57 @@ len_error:
return ret;
}
@ -99,11 +99,11 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+ return 0;
+}
+
static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
struct nvmem_cell *speedbin_nvmem,
char **pvs_name,
@@ -265,6 +318,10 @@ static const struct qcom_cpufreq_match_d
.get_version = qcom_cpufreq_ipq8074_name_version,
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -218,6 +271,10 @@ static const struct qcom_cpufreq_match_d
.genpd_names = qcs404_genpd_names,
};
+static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
@ -113,11 +113,11 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -409,6 +466,7 @@ static const struct of_device_id qcom_cp
@@ -362,6 +419,7 @@ static const struct of_device_id qcom_cp
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
+ { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },

23
target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch → target/linux/qualcommax/patches-6.1/0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
View File

@ -1,4 +1,4 @@
From df75a00c60c6e58bc36e4c63e9d7f1910412b132 Mon Sep 17 00:00:00 2001
From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 13 Oct 2023 19:20:02 +0200
Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
@ -16,6 +16,7 @@ will get created by NVMEM CPUFreq driver.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[ Viresh: Fixed rebase conflict. ]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
@ -24,9 +25,9 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -164,6 +164,7 @@ static const struct of_device_id blockli
{ .compatible = "ti,omap3", },
@@ -165,6 +165,7 @@ static const struct of_device_id blockli
{ .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,ipq8074", },
{ .compatible = "qcom,apq8064", },
@ -34,9 +35,9 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
{ .compatible = "qcom,msm8960", },
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -31,6 +31,11 @@
@@ -33,6 +33,11 @@
#include <dt-bindings/arm/qcom,ids.h>
#define IPQ6000_VERSION BIT(2)
+enum ipq8074_versions {
+ IPQ8074_HAWKEYE_VERSION = 0,
@ -46,8 +47,8 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -204,6 +209,44 @@ len_error:
return ret;
@@ -257,6 +262,44 @@ static int qcom_cpufreq_ipq6018_name_ver
return 0;
}
+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
@ -91,8 +92,8 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -218,6 +261,10 @@ static const struct qcom_cpufreq_match_d
.genpd_names = qcs404_genpd_names,
@@ -275,6 +318,10 @@ static const struct qcom_cpufreq_match_d
.get_version = qcom_cpufreq_ipq6018_name_version,
};
+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
@ -102,9 +103,9 @@ Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -363,6 +410,7 @@ static const struct of_device_id qcom_cp
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
@@ -421,6 +468,7 @@ static const struct of_device_id qcom_cp
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },

6
target/linux/qualcommax/patches-6.1/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch
View File

@ -19,9 +19,9 @@ Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -684,8 +684,8 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
@@ -685,8 +685,8 @@
compatible = "qcom,ipq8074-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
- clocks = <&a53pll>, <&xo>;
- clock-names = "pll", "xo";

52
target/linux/qualcommax/patches-6.1/0033-v6.2-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC.patch Normal file
View File

@ -0,0 +1,52 @@
From feeef118fda562cf9081edef8ad464d89db070f4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 27 Sep 2022 22:12:18 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node
The ARM timer is usually considered not part of SoC node, just like
other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927201218.1264506-2-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -510,14 +510,6 @@
clock-names = "xo";
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -769,6 +761,14 @@
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
wcss: wcss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;

605
target/linux/qualcommax/patches-6.1/0034-v6.3-arm64-dts-qcom-ipq6018-Sort-nodes-properly.patch Normal file
View File

@ -0,0 +1,605 @@
From 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:28 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Sort nodes properly
Order nodes by unit address if one exists and alphabetically otherwise.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 562 +++++++++++++-------------
1 file changed, 281 insertions(+), 281 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -87,6 +87,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq6018", "qcom,scm";
+ };
+ };
+
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -123,12 +129,6 @@
};
};
- firmware {
- scm {
- compatible = "qcom,scm-ipq6018", "qcom,scm";
- };
- };
-
pmuv8: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
@@ -166,6 +166,28 @@
};
};
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: glink-channel {
+ compatible = "qcom,rpm-ipq6018";
+ qcom,glink-channels = "rpm_requests";
+
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq6018_s2: s2 {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
@@ -179,6 +201,102 @@
dma-ranges;
compatible = "simple-bus";
+ qusb_phy_1: qusb@59000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x00059000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: ssphy@78000 {
+ compatible = "qcom,ipq6018-qmp-usb3-phy";
+ reg = <0x0 0x00078000 0x0 0x1c4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: phy@78200 {
+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
+ <0x0 0x00078400 0x0 0x200>, /* Rx */
+ <0x0 0x00078800 0x0 0x1f8>, /* PCS */
+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_0: qusb@79000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x00079000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ pcie_phy: phy@84000 {
+ compatible = "qcom,ipq6018-qmp-pcie-phy";
+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+
+ pcie_phy0: phy@84200 {
+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ #clock-cells = <0>;
+ };
+ };
+
+ mdio: mdio@90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
+ reg = <0x0 0x00090000 0x0 0x64>;
+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
+ clock-names = "gcc_mdio_ahb_clk";
+ status = "disabled";
+ };
+
prng: qrng@e1000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;
@@ -257,6 +375,41 @@
reg = <0x0 0x01937000 0x0 0x21000>;
};
+ usb2: usb@70f8800 {
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+ reg = <0x0 0x070F8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_SLEEP_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ clock-names = "core",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <24000000>;
+ resets = <&gcc GCC_USB1_BCR>;
+ status = "disabled";
+
+ dwc_1: usb@7000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x07000000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_1>;
+ phy-names = "usb2-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07884000 0x0 0x2b000>;
@@ -366,6 +519,49 @@
status = "disabled";
};
+ usb3: usb@8af8800 {
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+ reg = <0x0 0x08af8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <133330000>,
+ <24000000>;
+
+ resets = <&gcc GCC_USB0_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x08a00000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ clocks = <&xo>;
+ clock-names = "ref";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
#address-cells = <2>;
@@ -386,105 +582,6 @@
};
};
- pcie_phy: phy@84000 {
- compatible = "qcom,ipq6018-qmp-pcie-phy";
- reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&gcc GCC_PCIE0_AUX_CLK>,
- <&gcc GCC_PCIE0_AHB_CLK>;
- clock-names = "aux", "cfg_ahb";
-
- resets = <&gcc GCC_PCIE0_PHY_BCR>,
- <&gcc GCC_PCIE0PHY_PHY_BCR>;
- reset-names = "phy",
- "common";
-
- pcie_phy0: phy@84200 {
- reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
- <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
- <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
- <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_pcie0_pipe_clk_src";
- #clock-cells = <0>;
- };
- };
-
- pcie0: pci@20000000 {
- compatible = "qcom,pcie-ipq6018";
- reg = <0x0 0x20000000 0x0 0xf1d>,
- <0x0 0x20000f20 0x0 0xa8>,
- <0x0 0x20001000 0x0 0x1000>,
- <0x0 0x80000 0x0 0x4000>,
- <0x0 0x20100000 0x0 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
-
- device_type = "pci";
- linux,pci-domain = <0>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
- max-link-speed = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- phys = <&pcie_phy0>;
- phy-names = "pciephy";
-
- ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
- <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
-
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78
- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79
- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83
- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
- <&gcc GCC_PCIE0_AXI_M_CLK>,
- <&gcc GCC_PCIE0_AXI_S_CLK>,
- <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
- <&gcc PCIE0_RCHNG_CLK>;
- clock-names = "iface",
- "axi_m",
- "axi_s",
- "axi_bridge",
- "rchng";
-
- resets = <&gcc GCC_PCIE0_PIPE_ARES>,
- <&gcc GCC_PCIE0_SLEEP_ARES>,
- <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
- <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
- <&gcc GCC_PCIE0_AHB_ARES>,
- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
- <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
- reset-names = "pipe",
- "sleep",
- "sticky",
- "axi_m",
- "axi_s",
- "ahb",
- "axi_m_sticky",
- "axi_s_sticky";
-
- status = "disabled";
- };
-
watchdog@b017000 {
compatible = "qcom,kpss-wdt";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
@@ -617,147 +714,74 @@
};
};
- mdio: mdio@90000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
- reg = <0x0 0x00090000 0x0 0x64>;
- clocks = <&gcc GCC_MDIO_AHB_CLK>;
- clock-names = "gcc_mdio_ahb_clk";
- status = "disabled";
- };
-
- qusb_phy_1: qusb@59000 {
- compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x00059000 0x0 0x180>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "cfg_ahb", "ref";
-
- resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
- status = "disabled";
- };
-
- usb2: usb@70f8800 {
- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x070F8800 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clocks = <&gcc GCC_USB1_MASTER_CLK>,
- <&gcc GCC_USB1_SLEEP_CLK>,
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- clock-names = "core",
- "sleep",
- "mock_utmi";
-
- assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- assigned-clock-rates = <133330000>,
- <24000000>;
- resets = <&gcc GCC_USB1_BCR>;
- status = "disabled";
-
- dwc_1: usb@7000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x07000000 0x0 0xcd00>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_1>;
- phy-names = "usb2-phy";
- tx-fifo-resize;
- snps,is-utmi-l1-suspend;
- snps,hird-threshold = /bits/ 8 <0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- dr_mode = "host";
- };
- };
+ pcie0: pci@20000000 {
+ compatible = "qcom,pcie-ipq6018";
+ reg = <0x0 0x20000000 0x0 0xf1d>,
+ <0x0 0x20000f20 0x0 0xa8>,
+ <0x0 0x20001000 0x0 0x1000>,
+ <0x0 0x80000 0x0 0x4000>,
+ <0x0 0x20100000 0x0 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
- ssphy_0: ssphy@78000 {
- compatible = "qcom,ipq6018-qmp-usb3-phy";
- reg = <0x0 0x00078000 0x0 0x1c4>;
- #address-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ max-link-speed = <3>;
+ #address-cells = <3>;
#size-cells = <2>;
- ranges;
-
- clocks = <&gcc GCC_USB0_AUX_CLK>,
- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
-
- resets = <&gcc GCC_USB0_PHY_BCR>,
- <&gcc GCC_USB3PHY_0_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
-
- usb0_ssphy: phy@78200 {
- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
- <0x0 0x00078400 0x0 0x200>, /* Rx */
- <0x0 0x00078800 0x0 0x1f8>, /* PCS */
- <0x0 0x00078600 0x0 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_usb0_pipe_clk_src";
- };
- };
- qusb_phy_0: qusb@79000 {
- compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x00079000 0x0 0x180>;
- #phy-cells = <0>;
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
- clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "cfg_ahb", "ref";
+ ranges = <0x81000000 0 0x20200000 0 0x20200000
+ 0 0x10000>, /* downstream I/O */
+ <0x82000000 0 0x20220000 0 0x20220000
+ 0 0xfde0000>; /* non-prefetchable memory */
- resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
- status = "disabled";
- };
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
- usb3: usb@8af8800 {
- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x8af8800 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
- <&gcc GCC_USB0_MASTER_CLK>,
- <&gcc GCC_USB0_SLEEP_CLK>,
- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
- clock-names = "cfg_noc",
- "core",
- "sleep",
- "mock_utmi";
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+ <&gcc PCIE0_RCHNG_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
- assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
- <&gcc GCC_USB0_MASTER_CLK>,
- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
- assigned-clock-rates = <133330000>,
- <133330000>,
- <24000000>;
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky",
+ "axi_s_sticky";
- resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
-
- dwc_0: usb@8a00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x8a00000 0x0 0xcd00>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
- phy-names = "usb2-phy", "usb3-phy";
- clocks = <&xo>;
- clock-names = "ref";
- tx-fifo-resize;
- snps,is-utmi-l1-suspend;
- snps,hird-threshold = /bits/ 8 <0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- dr_mode = "host";
- };
};
};
@@ -792,26 +816,4 @@
#interrupt-cells = <2>;
};
};
-
- rpm-glink {
- compatible = "qcom,glink-rpm";
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: glink-channel {
- compatible = "qcom,rpm-ipq6018";
- qcom,glink-channels = "rpm_requests";
-
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq6018_s2: s2 {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
- };
- };
- };
};

92
target/linux/qualcommax/patches-6.1/0035-v6.3-arm64-dts-qcom-ipq6018-Add-remove-some-newlines.patch Normal file
View File

@ -0,0 +1,92 @@
From 6db9ed9a128cbae1423d043f3debd8bfa77783fd Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:29 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Add/remove some newlines
Some lines were broken very aggresively, presumably to fit under 80 chars
and some places could have used a newline, particularly between subsequent
nodes. Address all that and remove redundant comments near PCIe ranges
while at it so as not to exceed 100 chars needlessly.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -102,26 +102,31 @@
opp-microvolt = <725000>;
clock-latency-ns = <200000>;
};
+
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <787500>;
clock-latency-ns = <200000>;
};
+
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <862500>;
clock-latency-ns = <200000>;
};
+
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
opp-microvolt = <925000>;
clock-latency-ns = <200000>;
};
+
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <987500>;
clock-latency-ns = <200000>;
};
+
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1062500>;
@@ -131,8 +136,7 @@
pmuv8: pmu {
compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci: psci {
@@ -734,24 +738,18 @@
phys = <&pcie_phy0>;
phy-names = "pciephy";
- ranges = <0x81000000 0 0x20200000 0 0x20200000
- 0 0x10000>, /* downstream I/O */
- <0x82000000 0 0x20220000 0 0x20220000
- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
+ <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78
- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79
- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83
- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,

25
target/linux/qualcommax/patches-6.1/0036-v6.3-arm64-dts-qcom-ipq6018-Use-lowercase-hex.patch Normal file
View File

@ -0,0 +1,25 @@
From 7356ae3e10abd1d71f06ff0b8a8e72aa7c955c57 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:30 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Use lowercase hex
One value escaped my previous lowercase hexification. Take care of it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -381,7 +381,7 @@
usb2: usb@70f8800 {
compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x070F8800 0x0 0x400>;
+ reg = <0x0 0x070f8800 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;

28
target/linux/qualcommax/patches-6.1/0037-v6.3-arm64-dts-qcom-ipq6018-align-RPM-G-Link-node-with.patch Normal file
View File

@ -0,0 +1,28 @@
From 679ee73bbee28cab441008f8cca38160cc8f3d05 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 8 Feb 2023 11:15:39 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: align RPM G-Link node with
bindings
Bindings expect (and most of DTS use) the RPM G-Link node name to be
"rpm-requests".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208101545.45711-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -176,7 +176,7 @@
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
- rpm_requests: glink-channel {
+ rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq6018";
qcom,glink-channels = "rpm_requests";

27
target/linux/qualcommax/patches-6.1/0038-v6.4-arm64-dts-qcom-ipq6018-cp01-c1-drop-SPI-cs-select.patch Normal file
View File

@ -0,0 +1,27 @@
From afa8eb675fc6dd606783ed2350de90927d6fb9d3 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 8 Mar 2023 13:59:01 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select
The SPI controller nodes do not use/allow cs-select property:
ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -36,7 +36,6 @@
};
&blsp1_spi1 {
- cs-select = <0>;
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";

92
target/linux/qualcommax/patches-6.1/0039-v6.5-arm64-dts-qcom-add-few-more-reserved-memory-region.patch Normal file
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@ -0,0 +1,92 @@
From 0cd4e90cb2dec02ff859f5c98f744f43a23aea65 Mon Sep 17 00:00:00 2001
From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Date: Fri, 26 May 2023 16:36:53 +0530
Subject: [PATCH] arm64: dts: qcom: add few more reserved memory region
In IPQ SoCs, bootloader will collect the system RAM contents upon crash
for the post morterm analysis. If we don't reserve the memory region used
by bootloader, obviously linux will consume it and upon next boot on
crash, bootloader will be loaded in the same region, which will lead to
loose some of the data, sometimes we may miss out critical information.
So lets reserve the region used by the bootloader.
Similarly SBL copies some data into the reserved region and it will be
used in the crash scenario. So reserve 1MB for SBL as well.
While at it, drop the size padding in the reserved memory region,
wherever applicable.
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++--
2 files changed, 25 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -154,18 +154,28 @@
no-map;
};
+ bootloader@4a100000 {
+ reg = <0x0 0x4a100000 0x0 0x400000>;
+ no-map;
+ };
+
+ sbl@4a500000 {
+ reg = <0x0 0x4a500000 0x0 0x100000>;
+ no-map;
+ };
+
tz: memory@4a600000 {
- reg = <0x0 0x4a600000 0x0 0x00400000>;
+ reg = <0x0 0x4a600000 0x0 0x400000>;
no-map;
};
smem_region: memory@4aa00000 {
- reg = <0x0 0x4aa00000 0x0 0x00100000>;
+ reg = <0x0 0x4aa00000 0x0 0x100000>;
no-map;
};
q6_region: memory@4ab00000 {
- reg = <0x0 0x4ab00000 0x0 0x05500000>;
+ reg = <0x0 0x4ab00000 0x0 0x5500000>;
no-map;
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -85,17 +85,27 @@
#size-cells = <2>;
ranges;
+ bootloader@4a600000 {
+ reg = <0x0 0x4a600000 0x0 0x400000>;
+ no-map;
+ };
+
+ sbl@4aa00000 {
+ reg = <0x0 0x4aa00000 0x0 0x100000>;
+ no-map;
+ };
+
smem@4ab00000 {
compatible = "qcom,smem";
- reg = <0x0 0x4ab00000 0x0 0x00100000>;
+ reg = <0x0 0x4ab00000 0x0 0x100000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
memory@4ac00000 {
+ reg = <0x0 0x4ac00000 0x0 0x400000>;
no-map;
- reg = <0x0 0x4ac00000 0x0 0x00400000>;
};
};

49
target/linux/qualcommax/patches-6.1/0040-v6.5-arm64-dts-qcom-enable-the-download-mode-support.patch Normal file
View File

@ -0,0 +1,49 @@
From 9b2406aaba7841863ac041225316c1ec1c86ea36 Mon Sep 17 00:00:00 2001
From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Date: Fri, 26 May 2023 16:36:52 +0530
Subject: [PATCH] arm64: dts: qcom: enable the download mode support
Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the
download mode to collect the RAM dumps if system crashes, to perform
the post mortem analysis. Add support for the same.
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++
2 files changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -90,6 +90,7 @@
firmware {
scm {
compatible = "qcom,scm-ipq6018", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x6100>;
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -112,6 +112,7 @@
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x6100>;
};
};
@@ -386,6 +387,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1937000 {
+ compatible = "qcom,tcsr-ipq8074", "syscon";
+ reg = <0x01937000 0x21000>;
+ };
+
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,

29
target/linux/qualcommax/patches-6.1/0041-v6.5-arm64-dts-qcom-ipq6018-correct-qrng-unit-address.patch Normal file
View File

@ -0,0 +1,29 @@
From 085058786a7890dd44ec623fe5ac74db870f6b93 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 19 Apr 2023 23:18:39 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: correct qrng unit address
Match unit-address to reg entry to fix dtbs W=1 warnings:
Warning (simple_bus_reg): /soc/qrng@e1000: simple-bus unit address format error, expected "e3000"
Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230419211856.79332-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -312,7 +312,7 @@
status = "disabled";
};
- prng: qrng@e1000 {
+ prng: qrng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;

28
target/linux/qualcommax/patches-6.1/0042-v6.5-arm64-dts-qcom-ipq6018-add-unit-address-to-soc-node.patch Normal file
View File

@ -0,0 +1,28 @@
From 393595d4ffbd0a1fafd5548f8de1b8487a037cf2 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 20 Apr 2023 08:36:04 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: add unit address to soc node
"soc" node is supposed to have unit address:
Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230420063610.11068-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -209,7 +209,7 @@
hwlocks = <&tcsr_mutex 3>;
};
- soc: soc {
+ soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x0 0xffffffff>;

8
target/linux/qualcommax/patches-6.1/0037-v6.5-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch → target/linux/qualcommax/patches-6.1/0043-v6.5-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch
View File

@ -18,9 +18,9 @@ Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -179,6 +179,13 @@
dma-ranges;
compatible = "simple-bus";
@@ -312,6 +312,13 @@
status = "disabled";
};
+ qfprom: efuse@a4000 {
+ compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
@ -29,6 +29,6 @@ Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
+ #size-cells = <1>;
+ };
+
prng: qrng@e1000 {
prng: qrng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;

37
target/linux/qualcommax/patches-6.1/0044-v6.5-arm64-dts-qcom-ipq6018-drop-incorrect-SPI-bus.patch Normal file
View File

@ -0,0 +1,37 @@
From b8420d478aa3fc739fcdba6b4b945850b356cb3b Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Sun, 16 Apr 2023 14:37:25 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: drop incorrect SPI bus
spi-max-frequency
The spi-max-frequency property belongs to SPI devices, not SPI
controller:
ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 --
1 file changed, 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -458,7 +458,6 @@
#size-cells = <0>;
reg = <0x0 0x078b5000 0x0 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
@@ -473,7 +472,6 @@
#size-cells = <0>;
reg = <0x0 0x078b6000 0x0 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";

29
target/linux/qualcommax/patches-6.1/0045-v6.5-arm64-dts-qcom-ipq8074-drop-incorrect-SPI-bus.patch Normal file
View File

@ -0,0 +1,29 @@
From e6e0e706940b64e3a77e0a4840037692f109bd5f Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Sun, 16 Apr 2023 14:37:26 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: drop incorrect SPI bus
spi-max-frequency
The spi-max-frequency property belongs to SPI devices, not SPI
controller:
ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-2-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -487,7 +487,6 @@
#size-cells = <0>;
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";

27
target/linux/qualcommax/patches-6.1/0046-v6.6-clk-qcom-gcc-ipq6018-Use-floor-ops-for-sdcc-clocks.patch Normal file
View File

@ -0,0 +1,27 @@
From 56e5ae0116aef87273cf1812d608645b076e4f02 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 25 Apr 2023 12:11:49 +0300
Subject: [PATCH] clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocks
SDCC clocks must be rounded down to avoid overclocking the controller.
Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1682413909-24927-1-git-send-email-mantas@8devices.com
---
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -1702,7 +1702,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
.name = "usb0_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
.num_parents = 4,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};

2
target/linux/qualcommax/patches-6.1/0026-v6.5-clk-qcom-gcc-ipq6018-drop-redundant-F-define.patch → target/linux/qualcommax/patches-6.1/0047-v6.6-clk-qcom-gcc-ipq6018-drop-redundant-F-define.patch
View File

@ -1,4 +1,4 @@
From 1e8a314a1b87eaba496fcc6dc0efef573b3c186d Mon Sep 17 00:00:00 2001
From 923f7d678b2ae3d522543058514d5605c185633b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 17 Apr 2023 19:44:07 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: drop redundant F define

2
target/linux/qualcommax/patches-6.1/0033-v6.5-clk-qcom-gcc-ipq6018-update-UBI32-PLL.patch → target/linux/qualcommax/patches-6.1/0048-v6.6-clk-qcom-gcc-ipq6018-update-UBI32-PLL.patch
View File

@ -1,4 +1,4 @@
From 91e7c87f0ec1d644afb65cf3a16ded874c9d4ab9 Mon Sep 17 00:00:00 2001
From f4f0c8acee0e41c5fbae7a7ad06087668ddce0d6 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 26 May 2023 21:08:54 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: update UBI32 PLL

2
target/linux/qualcommax/patches-6.1/0034-v6.5-clk-qcom-gcc-ipq6018-remove-duplicate-initializers.patch → target/linux/qualcommax/patches-6.1/0049-v6.6-clk-qcom-gcc-ipq6018-remove-duplicate-initializers.patch
View File

@ -1,4 +1,4 @@
From 3f2fbfe6e4f6f2bdd1da8ef5aceba3945c4ada57 Mon Sep 17 00:00:00 2001
From 5ae7899765607e97e5eb34486336898c8d9ec654 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 1 Jun 2023 23:34:12 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: remove duplicate initializers

132
target/linux/qualcommax/patches-6.1/0050-v6.6-soc-qcom-Add-RPM-processor-subsystem-driver.patch Normal file
View File

@ -0,0 +1,132 @@
From 8ddfa81d090c71fd6cb3cb8ca1d420c0da33a575 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan@gerhold.net>
Date: Thu, 15 Jun 2023 18:50:42 +0200
Subject: [PATCH] soc: qcom: Add RPM processor/subsystem driver
Add a simple driver for the qcom,rpm-proc compatible that registers the
"smd-edge" and populates other children defined in the device tree.
Note that the DT schema belongs to the remoteproc subsystem while this
driver is added inside soc/qcom. I argue that the RPM *is* a remoteproc,
but as an implementation detail in Linux it can currently not benefit
from anything provided by the remoteproc subsystem. The RPM firmware is
usually already loaded and started by earlier components in the boot
chain and is not meant to be ever restarted.
To avoid breaking existing kernel configurations the driver is always
built when smd-rpm.c is also built. They belong closely together anyway.
To avoid build errors CONFIG_RPMSG_QCOM_SMD must be also built-in if
rpm-proc is.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-9-a07dcdefd918@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/soc/qcom/Kconfig | 1 +
drivers/soc/qcom/Makefile | 2 +-
drivers/soc/qcom/rpm-proc.c | 77 +++++++++++++++++++++++++++++++++++++
3 files changed, 79 insertions(+), 1 deletion(-)
create mode 100644 drivers/soc/qcom/rpm-proc.c
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -153,6 +153,7 @@ config QCOM_SMD_RPM
tristate "Qualcomm Resource Power Manager (RPM) over SMD"
depends on ARCH_QCOM || COMPILE_TEST
depends on RPMSG
+ depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
help
If you say yes to this option, support will be included for the
Resource Power Manager system found in the Qualcomm 8974 based
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_me
obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o
qcom_rpmh-y += rpmh-rsc.o
qcom_rpmh-y += rpmh.o
-obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
+obj-$(CONFIG_QCOM_SMD_RPM) += rpm-proc.o smd-rpm.o
obj-$(CONFIG_QCOM_SMEM) += smem.o
obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
--- /dev/null
+++ b/drivers/soc/qcom/rpm-proc.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/rpmsg/qcom_smd.h>
+
+static int rpm_proc_probe(struct platform_device *pdev)
+{
+ struct qcom_smd_edge *edge = NULL;
+ struct device *dev = &pdev->dev;
+ struct device_node *edge_node;
+ int ret;
+
+ edge_node = of_get_child_by_name(dev->of_node, "smd-edge");
+ if (edge_node) {
+ edge = qcom_smd_register_edge(dev, edge_node);
+ of_node_put(edge_node);
+ if (IS_ERR(edge))
+ return dev_err_probe(dev, PTR_ERR(edge),
+ "Failed to register smd-edge\n");
+ }
+
+ ret = devm_of_platform_populate(dev);
+ if (ret) {
+ dev_err(dev, "Failed to populate child devices: %d\n", ret);
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, edge);
+ return 0;
+err:
+ if (edge)
+ qcom_smd_unregister_edge(edge);
+ return ret;
+}
+
+static void rpm_proc_remove(struct platform_device *pdev)
+{
+ struct qcom_smd_edge *edge = platform_get_drvdata(pdev);
+
+ if (edge)
+ qcom_smd_unregister_edge(edge);
+}
+
+static const struct of_device_id rpm_proc_of_match[] = {
+ { .compatible = "qcom,rpm-proc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rpm_proc_of_match);
+
+static struct platform_driver rpm_proc_driver = {
+ .probe = rpm_proc_probe,
+ .remove_new = rpm_proc_remove,
+ .driver = {
+ .name = "qcom-rpm-proc",
+ .of_match_table = rpm_proc_of_match,
+ },
+};
+
+static int __init rpm_proc_init(void)
+{
+ return platform_driver_register(&rpm_proc_driver);
+}
+arch_initcall(rpm_proc_init);
+
+static void __exit rpm_proc_exit(void)
+{
+ platform_driver_unregister(&rpm_proc_driver);
+}
+module_exit(rpm_proc_exit);
+
+MODULE_DESCRIPTION("Qualcomm RPM processor/subsystem driver");
+MODULE_AUTHOR("Stephan Gerhold <stephan@gerhold.net>");
+MODULE_LICENSE("GPL");

93
target/linux/qualcommax/patches-6.1/0051-v6.6-arm64-dts-qcom-Add-rpm-proc-node-for-GLINK.patch Normal file
View File

@ -0,0 +1,93 @@
From 7e1acc8b92a3b67db1e5255adae2851d58d74434 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan@gerhold.net>
Date: Thu, 15 Jun 2023 18:50:44 +0200
Subject: [PATCH] arm64: dts: qcom: Add rpm-proc node for GLINK gplatforms
Rather than having the RPM GLINK channels as the only child of a dummy
top-level rpm-glink node, switch to representing the RPM as remoteproc
like all the other remoteprocs (modem DSP, ...).
This allows assigning additional subdevices to it like the MPM
interrupt-controller or rpm-master-stats.
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6375
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-11-a07dcdefd918@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++----
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++--
arch/arm64/boot/dts/qcom/msm8996.dtsi | 113 +++++++++----------
arch/arm64/boot/dts/qcom/msm8998.dtsi | 102 ++++++++---------
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 126 ++++++++++-----------
arch/arm64/boot/dts/qcom/qcs404.dtsi | 152 +++++++++++++-------------
arch/arm64/boot/dts/qcom/sdm630.dtsi | 132 +++++++++++-----------
arch/arm64/boot/dts/qcom/sm6115.dtsi | 128 +++++++++++-----------
arch/arm64/boot/dts/qcom/sm6125.dtsi | 140 ++++++++++++------------
arch/arm64/boot/dts/qcom/sm6375.dtsi | 126 ++++++++++-----------
10 files changed, 566 insertions(+), 529 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -145,6 +145,32 @@
method = "smc";
};
+ rpm: remoteproc {
+ compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
+
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-ipq6018";
+ qcom,glink-channels = "rpm_requests";
+
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq6018_s2: s2 {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -181,28 +207,6 @@
};
};
- rpm-glink {
- compatible = "qcom,glink-rpm";
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-ipq6018";
- qcom,glink-channels = "rpm_requests";
-
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq6018_s2: s2 {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
- };
- };
- };
-
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;

19
target/linux/qualcommax/patches-6.1/0135-arm64-dts-qcom-ipq6018-include-the-GPLL0-as-clock-pr.patch → target/linux/qualcommax/patches-6.1/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch
View File

@ -1,25 +1,28 @@
From a120815200adaf3ac28ccf3a1813c78b4be02cc4 Mon Sep 17 00:00:00 2001
From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001
From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Date: Thu, 14 Sep 2023 12:29:59 +0530
Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
provider for mailbox
While the kernel is booting up, APSS PLL will be running at 800MHz with
GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
configured to the rate based on the opp table and the source also will
be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
with this inclusion, CPU Freq correctly reports that CPU is running at
800MHz rather than 24MHz.
While the kernel is booting up, APSS clock / CPU clock will be running
at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
APSS PLL will be configured to the rate based on the opp table and the
source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
consume the GPLL0, with this inclusion, CPU Freq correctly reports that
CPU is running at 800MHz rather than 24MHz.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com
[bjorn: Updated commit message, as requested by Kathiravan]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -504,8 +504,8 @@
@@ -618,8 +618,8 @@
compatible = "qcom,ipq6018-apcs-apps-global";
reg = <0x0 0x0b111000 0x0 0x1000>;
#clock-cells = <1>;

57
target/linux/qualcommax/patches-6.1/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch Normal file
View File

@ -0,0 +1,57 @@
From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 21 Oct 2023 13:55:18 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock
QUP6 I2C clock is listed in the dt bindings but it was never included in
the GCC driver.
So lets add support for it, it is marked as criticial as it is used by RPM
to communicate to the external PMIC over I2C so this clock must not be
disabled.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -2120,6 +2120,26 @@ static struct clk_branch gcc_blsp1_qup5_
},
};
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+ .halt_reg = 0x07010,
+ .clkr = {
+ .enable_reg = 0x07010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup6_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ /*
+ * RPM uses QUP6 I2C to communicate with the external
+ * PMIC so it must not be disabled.
+ */
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0700c,
.clkr = {
@@ -4276,6 +4296,7 @@ static struct clk_regmap *gcc_ipq6018_cl
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,

16
target/linux/qualcommax/patches-6.1/0142-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch → target/linux/qualcommax/patches-6.1/0054-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -93,37 +93,49 @@
@@ -95,42 +95,49 @@
};
cpu_opp_table: opp-table-cpu {
@ -35,35 +35,35 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
+
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <787500>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
+
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <862500>;
+ opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
+
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
opp-microvolt = <925000>;
+ opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
+
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <987500>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
+
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1062500>;
@ -71,7 +71,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clock-latency-ns = <200000>;
};
};
@@ -189,6 +201,11 @@
@@ -321,6 +328,11 @@
reg = <0x0 0x000a4000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
@ -82,4 +82,4 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+ };
};
prng: qrng@e1000 {
prng: qrng@e3000 {

81
target/linux/qualcommax/patches-6.1/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch Normal file
View File

@ -0,0 +1,81 @@
From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Sun, 3 Dec 2023 23:39:14 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node
Add node to support all the QUP UART node controller inside of IPQ6018.
Some routers use these bus to connect Bluetooth chips.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -458,6 +458,26 @@
qcom,ee = <0>;
};
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78af000 0x0 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart2: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78b0000 0x0 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x078b1000 0x0 0x200>;
@@ -466,6 +486,36 @@
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
+ };
+
+ blsp1_uart4: serial@78b2000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x078b2000 0x0 0x200>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart5: serial@78b3000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78b3000 0x0 0x200>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart6: serial@78b4000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x078b4000 0x0 0x200>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
};
blsp1_spi1: spi@78b5000 {

95
target/linux/qualcommax/patches-6.1/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch Normal file
View File

@ -0,0 +1,95 @@
From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <quic_kriskura@quicinc.com>
Date: Fri, 26 Jan 2024 00:29:18 +0530
Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
On several QUSB2 Targets, the hs_phy_irq mentioned is actually
qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
to qusb2_phy for such targets.
In actuality, the hs_phy_irq is also present in these targets, but
kept in for debug purposes in hw test environments. This is not
triggered by default and its functionality is mutually exclusive
to that of qusb2_phy interrupt.
Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
Add missing ss_phy_irq on some targets which allows for remote
wakeup to work on a Super Speed link.
Also modify order of interrupts in accordance to bindings update.
Since driver looks up for interrupts by name and not by index, it
is safe to modify order of these interrupts in the DT.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++--
arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++--
arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++--
arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++----
arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++--
arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++--
8 files changed, 70 insertions(+), 14 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -430,6 +430,12 @@
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<24000000>;
+
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy";
+
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
@@ -628,6 +634,13 @@
<133330000>,
<24000000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -611,6 +611,13 @@
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB0_GDSC>;
resets = <&gcc GCC_USB0_BCR>;
@@ -653,6 +660,13 @@
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB1_GDSC>;
resets = <&gcc GCC_USB1_BCR>;

12
target/linux/qualcommax/patches-6.1/0138-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-compatib.patch → target/linux/qualcommax/patches-6.1/0057-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch
View File

@ -1,7 +1,7 @@
From a120815200adaf3ac28ccf3a1813c78b4be02cc4 Mon Sep 17 00:00:00 2001
From c3dc3d079d191c9149496b3c7fe1ece909386d93 Mon Sep 17 00:00:00 2001
From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Date: Tue, 5 Sep 2023 15:25:35 +0530
Subject: [PATCH v2 2/2] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible
Subject: [PATCH] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible
IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000.
The compatible string qcom,ipq6018-tcsr-mutex is mapped to
@ -11,13 +11,11 @@ and doesn't match the HW present in IPQ6018.
Remove IPQ6018 specific compatible string so that it fallsback to
of_tcsr_mutex data which maps to the correct configuration for IPQ6018.
Changes in v2:
- Updated commit message
- Added Fixes and stable tags
Cc: stable@vger.kernel.org
Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs")
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230905095535.1263113-3-quic_viswanat@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/hwspinlock/qcom_hwspinlock.c | 1 -
1 file changed, 1 deletion(-)

10
target/linux/qualcommax/patches-6.1/0140-arm64-dts-qcom-ipq6018-add-tsens-node.patch → target/linux/qualcommax/patches-6.1/0058-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch
View File

@ -1,19 +1,21 @@
From 946b1a565a60a04f8e5171a79a463f99485a3531 Mon Sep 17 00:00:00 2001
From 0b17197055b528da22e9385200e61b847b499d48 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Wed, 24 Jan 2024 15:07:24 +0200
Subject: [PATCH 2/3] arm64: dts: qcom: ipq6018: add tsens node
Date: Thu, 25 Jan 2024 11:04:11 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: add tsens node
IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add
node for it.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -193,6 +193,16 @@
@@ -342,6 +342,16 @@
clock-names = "core";
};

22
target/linux/qualcommax/patches-6.1/0141-arm64-dts-qcom-ipq6018-add-thermal-zones.patch → target/linux/qualcommax/patches-6.1/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch
View File

@ -1,14 +1,16 @@
From 92c65f959ec2b8d1ab26efe246b29ed538b45c86 Mon Sep 17 00:00:00 2001
From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Wed, 24 Jan 2024 15:10:43 +0200
Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add thermal zones
Date: Thu, 25 Jan 2024 11:04:12 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones
Add thermal zones to make use of thermal sensors data. For CPU zone,
add cooling device that uses CPU frequency scaling.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@ -53,11 +55,10 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
};
L2_0: l2-cache {
@@ -808,6 +813,122 @@
};
@@ -888,6 +893,122 @@
};
};
+
+ thermal-zones {
+ nss-top-thermal {
+ polling-delay-passive = <250>;
@ -173,6 +174,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
+ };
+ };
+ };
wcss: wcss-smp2p {
compatible = "qcom,smp2p";
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

4
target/linux/qualcommax/patches-6.1/0036-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch → target/linux/qualcommax/patches-6.1/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -3503,6 +3503,22 @@ static struct clk_branch gcc_prng_ahb_cl
@@ -3523,6 +3523,22 @@ static struct clk_branch gcc_prng_ahb_cl
},
};
@ -40,7 +40,7 @@ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.clkr = {
@@ -4341,6 +4357,7 @@ static struct clk_regmap *gcc_ipq6018_cl
@@ -4362,6 +4378,7 @@ static struct clk_regmap *gcc_ipq6018_cl
[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,

0
target/linux/qualcommax/patches-6.1/0035-v6.9-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ601.patch → target/linux/qualcommax/patches-6.1/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch
View File

22
target/linux/qualcommax/patches-6.1/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch
View File

@ -19,7 +19,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -85,6 +85,26 @@
@@ -85,6 +85,16 @@
#size-cells = <2>;
ranges;
@ -33,22 +33,12 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ reg = <0x0 0x4a400000 0x0 0x00200000>;
+ };
+
+ uboot@4a600000 {
+ no-map;
+ reg = <0x0 0x4a600000 0x0 0x00400000>;
+ };
+
+ sbl@4aa00000 {
+ no-map;
+ reg = <0x0 0x4aa00000 0x0 0x00100000>;
+ };
+
smem@4ab00000 {
compatible = "qcom,smem";
reg = <0x0 0x4ab00000 0x0 0x00100000>;
@@ -97,6 +117,21 @@
bootloader@4a600000 {
reg = <0x0 0x4a600000 0x0 0x400000>;
no-map;
@@ -107,6 +117,21 @@
reg = <0x0 0x4ac00000 0x0 0x400000>;
no-map;
reg = <0x0 0x4ac00000 0x0 0x00400000>;
};
+
+ q6_region: wcnss@4b000000 {

2
target/linux/qualcommax/patches-6.1/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -398,8 +398,8 @@
@@ -399,8 +399,8 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;

6
target/linux/qualcommax/patches-6.1/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -701,7 +701,7 @@
@@ -720,7 +720,7 @@
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
ranges = <0 0xb00a000 0xffd>;
@ -21,7 +21,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xffd>;
@@ -813,8 +813,7 @@
@@ -833,8 +833,7 @@
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
@ -31,7 +31,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142
@@ -875,8 +874,7 @@
@@ -895,8 +894,7 @@
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */

8
target/linux/qualcommax/patches-6.1/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch
View File

@ -16,7 +16,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -140,6 +140,32 @@
@@ -141,6 +141,32 @@
};
};
@ -49,8 +49,8 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
soc: soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -411,6 +437,11 @@
#hwlock-cells = <1>;
@@ -417,6 +443,11 @@
reg = <0x01937000 0x21000>;
};
+ tcsr_q6: syscon@1945000 {
@ -61,7 +61,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
@@ -915,6 +946,56 @@
@@ -935,6 +966,56 @@
"axi_s_sticky";
status = "disabled";
};

2
target/linux/qualcommax/patches-6.1/0121-arm64-dts-ipq8074-Add-WLAN-node.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -996,6 +996,117 @@
@@ -1016,6 +1016,117 @@
};
};
};

2
target/linux/qualcommax/patches-6.1/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -342,6 +342,113 @@
@@ -343,6 +343,113 @@
status = "disabled";
};

4
target/linux/qualcommax/patches-6.1/0137-arm64-dts-qcom-ipq6018-add-SDHCI-node.patch
View File

@ -13,8 +13,8 @@ Tested-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -264,6 +264,29 @@
reg = <0x0 0x01937000 0x0 0x21000>;
@@ -469,6 +469,29 @@
};
};
+ sdhc_1: mmc@7804000 {

18
target/linux/qualcommax/patches-6.1/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch
View File

@ -13,15 +13,15 @@ Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -841,6 +841,11 @@
regulator-max-microvolt = <1062500>;
regulator-always-on;
};
@@ -178,6 +178,11 @@
regulator-max-microvolt = <1062500>;
regulator-always-on;
};
+
+ ipq6018_l2: l2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ipq6018_l2: l2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
};
};
};

2
target/linux/qualcommax/patches-6.1/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -638,6 +638,102 @@
@@ -807,6 +807,102 @@
};
};

2
target/linux/qualcommax/patches-6.1/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -1057,6 +1057,7 @@
@@ -1155,6 +1155,7 @@
wcss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";

2
target/linux/qualcommax/patches-6.1/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -759,8 +759,8 @@
@@ -928,8 +928,8 @@
"wcss_reset",
"wcss_q6_reset";

2
target/linux/qualcommax/patches-6.1/0910-arm64-dts-qcom-ipq6018-change-voltage-to-perf-levels.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -99,42 +99,42 @@
@@ -106,42 +106,42 @@
opp-864000000 {
opp-hz = /bits/ 64 <864000000>;