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4108c0c1b6
- Mark patches as upstream - Backport more upstream changes - Handle conflicts and refresh patches Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
93 lines
2.9 KiB
Diff
93 lines
2.9 KiB
Diff
From 6db9ed9a128cbae1423d043f3debd8bfa77783fd Mon Sep 17 00:00:00 2001
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From: Konrad Dybcio <konrad.dybcio@linaro.org>
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Date: Mon, 2 Jan 2023 10:46:29 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq6018: Add/remove some newlines
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Some lines were broken very aggresively, presumably to fit under 80 chars
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and some places could have used a newline, particularly between subsequent
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nodes. Address all that and remove redundant comments near PCIe ranges
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while at it so as not to exceed 100 chars needlessly.
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Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
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1 file changed, 12 insertions(+), 14 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -102,26 +102,31 @@
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opp-microvolt = <725000>;
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clock-latency-ns = <200000>;
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};
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+
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <787500>;
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clock-latency-ns = <200000>;
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};
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+
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opp-1320000000 {
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opp-hz = /bits/ 64 <1320000000>;
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opp-microvolt = <862500>;
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clock-latency-ns = <200000>;
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};
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+
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opp-1440000000 {
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opp-hz = /bits/ 64 <1440000000>;
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opp-microvolt = <925000>;
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clock-latency-ns = <200000>;
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};
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+
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <987500>;
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clock-latency-ns = <200000>;
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};
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+
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1062500>;
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@@ -131,8 +136,7 @@
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pmuv8: pmu {
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compatible = "arm,cortex-a53-pmu";
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- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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- IRQ_TYPE_LEVEL_HIGH)>;
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+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci: psci {
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@@ -734,24 +738,18 @@
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phys = <&pcie_phy0>;
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phy-names = "pciephy";
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- ranges = <0x81000000 0 0x20200000 0 0x20200000
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- 0 0x10000>, /* downstream I/O */
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- <0x82000000 0 0x20220000 0 0x20220000
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- 0 0xfde0000>; /* non-prefetchable memory */
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+ ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
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+ <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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- interrupt-map = <0 0 0 1 &intc 0 75
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- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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- <0 0 0 2 &intc 0 78
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- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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- <0 0 0 3 &intc 0 79
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- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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- <0 0 0 4 &intc 0 83
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- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
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<&gcc GCC_PCIE0_AXI_M_CLK>,
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