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I noticed these changes when reviewing the 2011 Broadcom SDK. I haven't noticed any obvious changes in behavior with them applied; but thought I should at least pass them on. Signed-off-by: Nathan Hintz <nlhintz@hotmail.com> SVN-Revision: 34670
51 lines
1.7 KiB
Diff
51 lines
1.7 KiB
Diff
--- a/drivers/bcma/core.c
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+++ b/drivers/bcma/core.c
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@@ -43,6 +43,7 @@ int bcma_core_enable(struct bcma_device
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bcma_aread32(core, BCMA_IOCTL);
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bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+ bcma_aread32(core, BCMA_RESET_CTL);
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udelay(1);
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bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
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--- a/include/linux/bcma/bcma_driver_pci.h
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+++ b/include/linux/bcma/bcma_driver_pci.h
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@@ -179,6 +179,8 @@ struct pci_dev;
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#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
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#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
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+#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
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+
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/* PCIE Root Capability Register bits (Host mode only) */
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#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
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--- a/drivers/bcma/driver_pci_host.c
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+++ b/drivers/bcma/driver_pci_host.c
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@@ -430,7 +430,7 @@ void __devinit bcma_core_pci_hostmode_in
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/* Reset RC */
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usleep_range(3000, 5000);
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pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
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- usleep_range(1000, 2000);
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+ msleep(50);
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pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
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BCMA_CORE_PCI_CTL_RST_OE);
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@@ -492,6 +492,17 @@ void __devinit bcma_core_pci_hostmode_in
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bcma_core_pci_enable_crs(pc);
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+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
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+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
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+ u16 val16;
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+ bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
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+ &val16, sizeof(val16));
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+ val16 |= (2 << 5); /* Max payload size of 512 */
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+ val16 |= (2 << 12); /* MRRS 512 */
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+ bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
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+ &val16, sizeof(val16));
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+ }
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+
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/* Enable PCI bridge BAR0 memory & master access */
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tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
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