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2b1c6b21b5
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Also adds support for Raspberry Pi Compute Module 3 (untested). Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
74 lines
2.3 KiB
Diff
74 lines
2.3 KiB
Diff
From 0bd7afe408b2afd845f3b4971cfa641653716a12 Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 15:43:56 +0000
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Subject: [PATCH] clk: bcm2835: add missing PLL clock dividers
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 728436956aa172b24a3212295f8b53feb6479f32)
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---
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drivers/clk/bcm/clk-bcm2835.c | 32 ++++++++++++++++++++++++++++++++
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include/dt-bindings/clock/bcm2835.h | 5 +++++
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2 files changed, 37 insertions(+)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1387,6 +1387,22 @@ static const struct bcm2835_clk_desc clk
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.load_mask = CM_PLLA_LOADPER,
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.hold_mask = CM_PLLA_HOLDPER,
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.fixed_divider = 1),
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+ [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
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+ .name = "plla_dsi0",
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+ .source_pll = "plla",
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+ .cm_reg = CM_PLLA,
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+ .a2w_reg = A2W_PLLA_DSI0,
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+ .load_mask = CM_PLLA_LOADDSI0,
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+ .hold_mask = CM_PLLA_HOLDDSI0,
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+ .fixed_divider = 1),
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+ [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
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+ .name = "plla_ccp2",
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+ .source_pll = "plla",
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+ .cm_reg = CM_PLLA,
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+ .a2w_reg = A2W_PLLA_CCP2,
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+ .load_mask = CM_PLLA_LOADCCP2,
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+ .hold_mask = CM_PLLA_HOLDCCP2,
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+ .fixed_divider = 1),
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/* PLLB is used for the ARM's clock. */
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[BCM2835_PLLB] = REGISTER_PLL(
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@@ -1501,6 +1517,22 @@ static const struct bcm2835_clk_desc clk
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.load_mask = CM_PLLD_LOADPER,
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.hold_mask = CM_PLLD_HOLDPER,
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.fixed_divider = 1),
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+ [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
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+ .name = "plld_dsi0",
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+ .source_pll = "plld",
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+ .cm_reg = CM_PLLD,
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+ .a2w_reg = A2W_PLLD_DSI0,
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+ .load_mask = CM_PLLD_LOADDSI0,
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+ .hold_mask = CM_PLLD_HOLDDSI0,
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+ .fixed_divider = 1),
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+ [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
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+ .name = "plld_dsi1",
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+ .source_pll = "plld",
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+ .cm_reg = CM_PLLD,
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+ .a2w_reg = A2W_PLLD_DSI1,
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+ .load_mask = CM_PLLD_LOADDSI1,
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+ .hold_mask = CM_PLLD_HOLDDSI1,
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+ .fixed_divider = 1),
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/*
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* PLLH is used to supply the pixel clock or the AUX clock for the
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--- a/include/dt-bindings/clock/bcm2835.h
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+++ b/include/dt-bindings/clock/bcm2835.h
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@@ -45,3 +45,8 @@
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#define BCM2835_CLOCK_PERI_IMAGE 29
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#define BCM2835_CLOCK_PWM 30
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#define BCM2835_CLOCK_PCM 31
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+
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+#define BCM2835_PLLA_DSI0 32
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+#define BCM2835_PLLA_CCP2 33
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+#define BCM2835_PLLD_DSI0 34
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+#define BCM2835_PLLD_DSI1 35
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