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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
48 lines
1.8 KiB
Diff
48 lines
1.8 KiB
Diff
From 866aab825ad10675b1e98004aec19127ec16b2b3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
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Date: Mon, 23 Sep 2019 14:28:42 +0300
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Subject: [PATCH] MLKU-123-1 crypto: caam - add support for i.mx8mm, mn
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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TODO:
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1. clarify logic wrt. virtualization and DECORSR - see e-mail thread:
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"Register-based interface - DECORSR with virtualization disabled"
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2. check whether the clocks are identical for all mScale parts,
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and if they do use a single "i.MX8M*" entry in clocks array.
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Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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---
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drivers/crypto/caam/ctrl.c | 8 ++++++--
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1 file changed, 6 insertions(+), 2 deletions(-)
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--- a/drivers/crypto/caam/ctrl.c
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+++ b/drivers/crypto/caam/ctrl.c
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@@ -99,10 +99,12 @@ static inline int run_descriptor_deco0(s
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if (ctrlpriv->virt_en == 1 ||
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/*
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- * Apparently on i.MX8MQ it doesn't matter if virt_en == 1
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+ * Apparently on i.MX8MQ, 8MM, 8MN it doesn't matter if virt_en == 1
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* and the following steps should be performed regardless
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*/
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- of_machine_is_compatible("fsl,imx8mq")) {
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+ of_machine_is_compatible("fsl,imx8mq") ||
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+ of_machine_is_compatible("fsl,imx8mm") ||
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+ of_machine_is_compatible("fsl,imx8mn")) {
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clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
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while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
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@@ -514,6 +516,8 @@ static const struct soc_device_attribute
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{ .soc_id = "i.MX6*", .data = &caam_imx6_data },
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{ .soc_id = "i.MX7*", .data = &caam_imx7_data },
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{ .soc_id = "i.MX8MQ", .data = &caam_imx7_data },
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+ { .soc_id = "i.MX8MM", .data = &caam_imx7_data },
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+ { .soc_id = "i.MX8MN", .data = &caam_imx7_data },
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{ .family = "Freescale i.MX" },
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{ /* sentinel */ }
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};
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