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f9b8328d79
Add the ranges property to the PCI bridges where missing. Add the unit address to PCI bridge where missing. Rework the complete rt3883 pci node. Drop the PCI unit nodes from the dtsi. They are not used by any dts file and should be rather in the dts than in the SoC dtsi. Express the PCI-PCI bridge in a clean devicetree syntax. The ralink,pci-slot isn't used by any driver, drop it. Move the pci interrupt controller out of the pci node. It doesn't share the same reg and therefore should be an independent/SoC child node. Move the pci related rt3883 pinctrl setting to the dtsi instead of defining the very same for each rt3883 board. If the device_type property is used for PCI units, the unit is treated as pci bridge which it isn't. Drop it for PCI units. Reference pci-bridges or the pci node defined in the dtsi instead of recreating the whole node hierarchy. It allows to change the referenced node in the dtsi without the need to touch all dts. Fix the PCI(e) wireless unit addresses. All our PCI(e) wireless chips are the first device on the bus. The unit address has to be the bus address instead of the PCI vendor/device id. Signed-off-by: Mathias Kresin <dev@kresin.me>
180 lines
3.7 KiB
Plaintext
180 lines
3.7 KiB
Plaintext
/*
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* BSD LICENSE
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*
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* Copyright (C) 2018 Piotr Dymacz <pepe2k@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of any
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "alfa-network,ac1200rm", "ralink,mt7620a-soc";
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model = "ALFA Network AC1200RM";
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aliases {
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led-status = &led_wps;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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wlan2g {
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label = "ac1200rm:green:wlan2g";
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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};
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led_wps: wps {
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label = "ac1200rm:green:wps";
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&ehci {
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status = "okay";
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};
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ðernet {
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mtd-mac-address = <&factory 0x28>;
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mediatek,portmap = "llllw";
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pinctrl-names = "default";
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pinctrl-0 = <&ephy_pins>;
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&gsw {
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mediatek,port4 = "ephy";
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};
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&ohci {
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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led {
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led-sources = <2>;
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led-active-low;
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};
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "nd_sd", "spi refclk", "wled";
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ralink,function = "gpio";
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};
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};
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x1000>;
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};
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partition@031000 {
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label = "config";
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reg = <0x31000 0xf000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "firmware";
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reg = <0x50000 0xfb0000>;
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};
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};
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0>;
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};
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