mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 14:13:16 +00:00
cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
63 lines
1.9 KiB
Diff
63 lines
1.9 KiB
Diff
From 0d4749abb6f7d042643ba1aa27a7388e8290b6f5 Mon Sep 17 00:00:00 2001
|
|
From: Li Jun <jun.li@nxp.com>
|
|
Date: Tue, 16 Apr 2019 14:02:38 +0800
|
|
Subject: [PATCH] usb: dwc3: use suspend clock from dt to set power down scale
|
|
|
|
Since the new dwc3 use bulk clks including the suspend clk, so we can
|
|
use it to calculate the power down scale value.
|
|
|
|
Acked-by: Peter Chen <peter.chen@nxp.com>
|
|
Signed-off-by: Li Jun <jun.li@nxp.com>
|
|
---
|
|
drivers/usb/dwc3/core.c | 21 +++++++++++++++++++++
|
|
drivers/usb/dwc3/core.h | 1 +
|
|
2 files changed, 22 insertions(+)
|
|
|
|
--- a/drivers/usb/dwc3/core.c
|
|
+++ b/drivers/usb/dwc3/core.c
|
|
@@ -894,6 +894,25 @@ static void dwc3_set_incr_burst_type(str
|
|
dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
|
|
}
|
|
|
|
+static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
|
|
+{
|
|
+ u32 reg, scale;
|
|
+
|
|
+ if (dwc->num_clks == 0)
|
|
+ return;
|
|
+
|
|
+ /*
|
|
+ * The power down scale field specifies how many suspend_clk
|
|
+ * periods fit into a 16KHz clock period. When performing
|
|
+ * the division, round up the remainder.
|
|
+ */
|
|
+ scale = DIV_ROUND_UP(clk_get_rate(dwc->clks[2].clk), 16384);
|
|
+ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
+ reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
|
|
+ reg |= DWC3_GCTL_PWRDNSCALE(scale);
|
|
+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
+}
|
|
+
|
|
/**
|
|
* dwc3_core_init - Low-level initialization of DWC3 Core
|
|
* @dwc: Pointer to our controller context structure
|
|
@@ -918,6 +937,8 @@ static int dwc3_core_init(struct dwc3 *d
|
|
dwc->maximum_speed = USB_SPEED_HIGH;
|
|
}
|
|
|
|
+ dwc3_set_power_down_clk_scale(dwc);
|
|
+
|
|
ret = dwc3_phy_setup(dwc);
|
|
if (ret)
|
|
goto err0;
|
|
--- a/drivers/usb/dwc3/core.h
|
|
+++ b/drivers/usb/dwc3/core.h
|
|
@@ -223,6 +223,7 @@
|
|
|
|
/* Global Configuration Register */
|
|
#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
|
|
+#define DWC3_GCTL_PWRDNSCALE_MASK DWC3_GCTL_PWRDNSCALE(0x1fff)
|
|
#define DWC3_GCTL_U2RSTECN BIT(16)
|
|
#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
|
|
#define DWC3_GCTL_CLK_BUS (0)
|