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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
141 lines
4.5 KiB
Diff
141 lines
4.5 KiB
Diff
From 5f62951fba63a9f9cfff564209426bdea5fcc371 Mon Sep 17 00:00:00 2001
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From: Alex Marginean <alexandru.marginean@nxp.com>
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Date: Tue, 27 Aug 2019 15:16:56 +0300
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Subject: [PATCH] drivers: net: phy: aquantia: enable AQR112 and AQR412
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Adds support for AQR112 and AQR412 which is mostly based on existing code
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with the addition of code configuring the protocol on system side.
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This allows changing the system side protocol without having to deploy a
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different firmware on the PHY.
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Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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---
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drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 88 insertions(+)
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--- a/drivers/net/phy/aquantia_main.c
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+++ b/drivers/net/phy/aquantia_main.c
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@@ -22,6 +22,8 @@
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#define PHY_ID_AQR107 0x03a1b4e0
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#define PHY_ID_AQCS109 0x03a1b5c2
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#define PHY_ID_AQR405 0x03a1b4b0
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+#define PHY_ID_AQR112 0x03a1b662
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+#define PHY_ID_AQR412 0x03a1b712
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#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
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@@ -121,6 +123,29 @@
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
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+/* registers in MDIO_MMD_VEND1 region */
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+#define AQUANTIA_VND1_GLOBAL_SC 0x000
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+#define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb)
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+
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+/* global start rate, the protocol associated with this speed is used by default
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+ * on SI.
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+ */
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+#define AQUANTIA_VND1_GSTART_RATE 0x31a
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+#define AQUANTIA_VND1_GSTART_RATE_OFF 0
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+#define AQUANTIA_VND1_GSTART_RATE_100M 1
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+#define AQUANTIA_VND1_GSTART_RATE_1G 2
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+#define AQUANTIA_VND1_GSTART_RATE_10G 3
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+#define AQUANTIA_VND1_GSTART_RATE_2_5G 4
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+#define AQUANTIA_VND1_GSTART_RATE_5G 5
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+
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+/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
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+#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
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+#define AQUANTIA_VND1_GSYSCFG_100M 0
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+#define AQUANTIA_VND1_GSYSCFG_1G 1
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+#define AQUANTIA_VND1_GSYSCFG_2_5G 2
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+#define AQUANTIA_VND1_GSYSCFG_5G 3
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+#define AQUANTIA_VND1_GSYSCFG_10G 4
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+
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struct aqr107_hw_stat {
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const char *name;
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int reg;
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@@ -241,6 +266,51 @@ static int aqr_config_aneg(struct phy_de
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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+static struct {
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+ u16 syscfg;
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+ int cnt;
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+ u16 start_rate;
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+} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {
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+ [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
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+ AQUANTIA_VND1_GSTART_RATE_1G},
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+ [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
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+ AQUANTIA_VND1_GSTART_RATE_2_5G},
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+ [PHY_INTERFACE_MODE_XGMII] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
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+ AQUANTIA_VND1_GSTART_RATE_10G},
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+ [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
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+ AQUANTIA_VND1_GSTART_RATE_10G},
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+};
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+
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+/* Sets up protocol on system side before calling aqr_config_aneg */
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+static int aqr_config_aneg_set_prot(struct phy_device *phydev)
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+{
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+ int if_type = phydev->interface;
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+ int i;
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+
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+ if (!aquantia_syscfg[if_type].cnt)
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+ return 0;
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+
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+ /* set PHY in low power mode so we can configure protocols */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
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+ AQUANTIA_VND1_GLOBAL_SC_LP);
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+ mdelay(10);
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+
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+ /* set the default rate to enable the SI link */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
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+ aquantia_syscfg[if_type].start_rate);
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+
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+ for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
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+ AQUANTIA_VND1_GSYSCFG_BASE + i,
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+ aquantia_syscfg[if_type].syscfg);
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+
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+ /* wake PHY back up */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
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+ mdelay(10);
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+
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+ return aqr_config_aneg(phydev);
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+}
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+
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static int aqr_config_intr(struct phy_device *phydev)
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{
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bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
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@@ -682,6 +752,22 @@ static struct phy_driver aqr_driver[] =
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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+{
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+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
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+ .name = "Aquantia AQR112",
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+ .config_aneg = aqr_config_aneg_set_prot,
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+ .config_intr = aqr_config_intr,
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+ .ack_interrupt = aqr_ack_interrupt,
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+ .read_status = aqr_read_status,
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+},
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+{
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+ PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
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+ .name = "Aquantia AQR412",
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+ .config_aneg = aqr_config_aneg_set_prot,
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+ .config_intr = aqr_config_intr,
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+ .ack_interrupt = aqr_ack_interrupt,
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+ .read_status = aqr_read_status,
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+},
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};
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module_phy_driver(aqr_driver);
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@@ -694,6 +780,8 @@ static struct mdio_device_id __maybe_unu
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
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+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
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+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
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{ }
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};
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