mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
e504fdae4e
Add pending patches from Alexander 'lynxis' Couzens which are required for RealTek NBase-T PHYs or SFP+ cages to work when connected to the SGMII interface provided by recent MediaTek SoCs [1]. The patches for MT753x fix link speed limitation on CPU ports observed by many users which is due to reset being carried out wrongly [2]. [1]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669488&state=* [2]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669486&state=* Signed-off-by: Daniel Golle <daniel@makrotopia.org>
66 lines
2.1 KiB
Diff
66 lines
2.1 KiB
Diff
From 9daea9b71d060d93d7394ac465b2e5ee0b7e7bca Mon Sep 17 00:00:00 2001
|
|
From: Alexander Couzens <lynxis@fe80.eu>
|
|
Date: Mon, 15 Aug 2022 16:02:01 +0200
|
|
Subject: [PATCH 06/10] net: mtk_sgmii: ensure the SGMII PHY is powered down on
|
|
configuration
|
|
|
|
The code expect the PHY to be in power down (which is only true after reset).
|
|
Allow the changes of SGMII parameters more than once.
|
|
---
|
|
drivers/net/ethernet/mediatek/mtk_sgmii.c | 16 +++++++++++++++-
|
|
1 file changed, 15 insertions(+), 1 deletion(-)
|
|
|
|
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
|
@@ -7,6 +7,7 @@
|
|
*
|
|
*/
|
|
|
|
+#include <linux/delay.h>
|
|
#include <linux/mfd/syscon.h>
|
|
#include <linux/of.h>
|
|
#include <linux/phylink.h>
|
|
@@ -24,6 +25,9 @@ static int mtk_pcs_setup_mode_an(struct
|
|
{
|
|
unsigned int val;
|
|
|
|
+ /* PHYA power down */
|
|
+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
|
|
+
|
|
/* Setup the link timer and QPHY power up inside SGMIISYS */
|
|
regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
|
|
SGMII_LINK_TIMER_DEFAULT);
|
|
@@ -36,6 +40,10 @@ static int mtk_pcs_setup_mode_an(struct
|
|
val |= SGMII_AN_RESTART;
|
|
regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
|
|
|
|
+ /* Release PHYA power down state
|
|
+ * unknown how much the QPHY needs but it is racy without a sleep
|
|
+ */
|
|
+ usleep_range(50, 100);
|
|
regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
|
|
|
|
return 0;
|
|
@@ -50,6 +58,9 @@ static int mtk_pcs_setup_mode_force(stru
|
|
{
|
|
unsigned int val;
|
|
|
|
+ /* PHYA power down */
|
|
+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
|
|
+
|
|
regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
|
|
val &= ~RG_PHY_SPEED_MASK;
|
|
if (interface == PHY_INTERFACE_MODE_2500BASEX)
|
|
@@ -67,7 +78,10 @@ static int mtk_pcs_setup_mode_force(stru
|
|
val |= SGMII_SPEED_1000;
|
|
regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
|
|
|
|
- /* Release PHYA power down state */
|
|
+ /* Release PHYA power down state
|
|
+ * unknown how much the QPHY needs but it is racy without a sleep
|
|
+ */
|
|
+ usleep_range(50, 100);
|
|
regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
|
|
|
|
return 0;
|