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kernel: add pending mtk_sgmii and phy improvements from @lynxis
Add pending patches from Alexander 'lynxis' Couzens which are required for RealTek NBase-T PHYs or SFP+ cages to work when connected to the SGMII interface provided by recent MediaTek SoCs [1]. The patches for MT753x fix link speed limitation on CPU ports observed by many users which is due to reset being carried out wrongly [2]. [1]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669488&state=* [2]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669486&state=* Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
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target/linux/generic/pending-5.15
721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch722-net-mt7531-only-do-PLL-once-after-the-reset.patch723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch724-net-mtk_sgmii-implement-mtk_pcs_ops.patch725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch726-net-mtk_sgmii-ensure-the-SGMII-PHY-is-powered-down-o.patch727-net-mtk_sgmii-mtk_pcs_setup_mode_an-don-t-rely-on-re.patch728-net-mtk_sgmii-set-the-speed-according-to-the-phy-int.patch729-net-mtk_eth_soc-improve-comment.patch730-mtk_sgmii-enable-PCS-polling-to-allow-SFP-work.patch
@ -0,0 +1,101 @@
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From ace6abaa0f9203083fe4c0a6a74da2d96410b625 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Sat, 13 Aug 2022 12:49:33 +0200
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Subject: [PATCH 01/10] net: phy: realtek: rtl8221: allow to configure SERDES
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mode
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The rtl8221 supports multiple SERDES modes:
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- SGMII
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- 2500base-x
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- HiSGMII
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Further it supports rate adaption on SERDES links to allow
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slow ethernet speeds (10/100/1000mbit) to work on 2500base-x/HiSGMII
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links without reducing the SERDES speed.
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When operating without rate adapters the SERDES link will follow the
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ethernet speed.
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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---
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drivers/net/phy/realtek.c | 48 +++++++++++++++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -53,6 +53,15 @@
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RTL8201F_ISR_LINK)
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#define RTL8201F_IER 0x13
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+#define RTL8221B_MMD_SERDES_CTRL MDIO_MMD_VEND1
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+#define RTL8221B_MMD_PHY_CTRL MDIO_MMD_VEND2
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+#define RTL8221B_SERDES_OPTION 0x697a
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+#define RTL8221B_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
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+#define RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII 0
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+#define RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII 1
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+#define RTL8221B_SERDES_OPTION_MODE_2500BASEX 2
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+#define RTL8221B_SERDES_OPTION_MODE_HISGMII 3
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+
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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@@ -841,6 +850,43 @@ static irqreturn_t rtl9000a_handle_inter
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return IRQ_HANDLED;
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}
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+static int rtl8221b_config_init(struct phy_device *phydev)
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+{
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+ u16 option_mode;
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+
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+ switch (phydev->interface) {
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+ case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ option_mode = RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII;
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+ break;
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+ default:
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+ return 0;
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+ }
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+
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL,
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+ 0x75f3, 0);
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+
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+ phy_modify_mmd_changed(phydev, RTL8221B_MMD_SERDES_CTRL,
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+ RTL8221B_SERDES_OPTION,
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+ RTL8221B_SERDES_OPTION_MODE_MASK, option_mode);
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+ switch (option_mode) {
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+ case RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII:
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+ case RTL8221B_SERDES_OPTION_MODE_2500BASEX:
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd455);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
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+ break;
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+ case RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII:
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+ case RTL8221B_SERDES_OPTION_MODE_HISGMII:
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd433);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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static struct phy_driver realtek_drvs[] = {
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{
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PHY_ID_MATCH_EXACT(0x00008201),
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@@ -981,6 +1027,7 @@ static struct phy_driver realtek_drvs[]
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PHY_ID_MATCH_EXACT(0x001cc849),
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.name = "RTL8221B-VB-CG 2.5Gbps PHY",
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.get_features = rtl822x_get_features,
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+ .config_init = rtl8221b_config_init,
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.config_aneg = rtl822x_config_aneg,
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.read_status = rtl822x_read_status,
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.suspend = genphy_suspend,
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@@ -992,6 +1039,7 @@ static struct phy_driver realtek_drvs[]
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.name = "RTL8221B-VM-CG 2.5Gbps PHY",
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.get_features = rtl822x_get_features,
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.config_aneg = rtl822x_config_aneg,
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+ .config_init = rtl8221b_config_init,
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.read_status = rtl822x_read_status,
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.suspend = genphy_suspend,
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.resume = rtlgen_resume,
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@ -0,0 +1,67 @@
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From 9fec662b54fc956b776df15c704e996c61292850 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Sat, 13 Aug 2022 13:05:09 +0200
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Subject: [PATCH 02/10] net: mt7531: only do PLL once after the reset
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Move the PLL init of the switch out of the pad configuration of the port
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6 (usally cpu port).
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Fix a unidirectional 100 mbit limitation on 1 gbit or 2.5 gbit links for
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outbound traffic on port 5 or port 6.
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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---
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drivers/net/dsa/mt7530.c | 15 +++++++++------
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1 file changed, 9 insertions(+), 6 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -506,14 +506,19 @@ static bool mt7531_dual_sgmii_supported(
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static int
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mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
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{
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- struct mt7530_priv *priv = ds->priv;
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+ return 0;
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+}
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+
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+static void
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+mt7531_pll_setup(struct mt7530_priv *priv)
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+{
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u32 top_sig;
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u32 hwstrap;
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u32 xtal;
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u32 val;
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if (mt7531_dual_sgmii_supported(priv))
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- return 0;
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+ return;
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val = mt7530_read(priv, MT7531_CREV);
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top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
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@@ -592,8 +597,6 @@ mt7531_pad_setup(struct dsa_switch *ds,
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val |= EN_COREPLL;
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mt7530_write(priv, MT7531_PLLGP_EN, val);
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usleep_range(25, 35);
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-
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- return 0;
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}
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static void
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@@ -2326,6 +2329,8 @@ mt7531_setup(struct dsa_switch *ds)
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SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
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SYS_CTRL_REG_RST);
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+ mt7531_pll_setup(priv);
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+
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if (mt7531_dual_sgmii_supported(priv)) {
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priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
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@@ -2882,8 +2887,6 @@ mt7531_cpu_port_config(struct dsa_switch
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case 6:
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interface = PHY_INTERFACE_MODE_2500BASEX;
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- mt7531_pad_setup(ds, interface);
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-
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priv->p6_interface = interface;
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break;
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default:
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@ -0,0 +1,28 @@
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From 3fb8841513c4ec3a2e5d366df86230c45f239a57 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Sat, 13 Aug 2022 13:08:22 +0200
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Subject: [PATCH 03/10] net: mt7531: ensure all MACs are powered down before
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reset
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The datasheet [1] explicit describes it as requirement for a reset.
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[1] MT7531 Reference Manual for Development Board rev 1.0, page 735
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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---
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drivers/net/dsa/mt7530.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -2324,6 +2324,10 @@ mt7531_setup(struct dsa_switch *ds)
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return -ENODEV;
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}
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+ /* all MACs must be forced link-down before sw reset */
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+ for (i = 0; i < MT7530_NUM_PORTS; i++)
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+ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
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+
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/* Reset the switch through internal reset */
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mt7530_write(priv, MT7530_SYS_CTRL,
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SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
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@ -0,0 +1,44 @@
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From cbfed00575d15eafd85efd9619b7ecc0836a4aa7 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Sat, 13 Aug 2022 14:42:12 +0200
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Subject: [PATCH 04/10] net: mtk_sgmii: implement mtk_pcs_ops
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Implement mtk_pcs_ops for the SGMII pcs to read the current state
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of the hardware.
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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[added DUPLEX_FULL]
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -122,10 +122,26 @@ static void mtk_pcs_link_up(struct phyli
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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}
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+static void mtk_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state)
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+{
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+ struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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+ unsigned int val;
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+
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+ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
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+ state->speed = val & RG_PHY_SPEED_3_125G ? SPEED_2500 : SPEED_1000;
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+
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+ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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+ state->an_complete = !!(val & SGMII_AN_COMPLETE);
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+ state->link = !!(val & SGMII_LINK_STATYS);
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+ state->duplex = DUPLEX_FULL;
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+ state->pause = 0;
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+}
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+
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static const struct phylink_pcs_ops mtk_pcs_ops = {
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.pcs_config = mtk_pcs_config,
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.pcs_an_restart = mtk_pcs_restart_an,
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.pcs_link_up = mtk_pcs_link_up,
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+ .pcs_get_state = mtk_pcs_get_state,
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};
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int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
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@ -0,0 +1,39 @@
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From 7f75f43fe2159123baa101fcc8c6faa0b0a4c598 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Sat, 13 Aug 2022 14:48:51 +0200
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Subject: [PATCH 05/10] net: mtk_sgmii: fix powering up the SGMII phy
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There are certain race condition when the SGMII_PHYA_PWD register still
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contains 0x9 which prevents the SGMII from working properly.
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The SGMII still shows link but no traffic can flow.
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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---
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 8 ++------
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1 file changed, 2 insertions(+), 6 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -36,9 +36,7 @@ static int mtk_pcs_setup_mode_an(struct
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val |= SGMII_AN_RESTART;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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- val &= ~SGMII_PHYA_PWD;
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- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return 0;
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@@ -70,9 +68,7 @@ static int mtk_pcs_setup_mode_force(stru
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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/* Release PHYA power down state */
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- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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- val &= ~SGMII_PHYA_PWD;
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- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return 0;
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}
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@ -0,0 +1,65 @@
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From 9daea9b71d060d93d7394ac465b2e5ee0b7e7bca Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Mon, 15 Aug 2022 16:02:01 +0200
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Subject: [PATCH 06/10] net: mtk_sgmii: ensure the SGMII PHY is powered down on
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configuration
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The code expect the PHY to be in power down (which is only true after reset).
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Allow the changes of SGMII parameters more than once.
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---
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 16 +++++++++++++++-
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1 file changed, 15 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -7,6 +7,7 @@
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*
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*/
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+#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/phylink.h>
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@@ -24,6 +25,9 @@ static int mtk_pcs_setup_mode_an(struct
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{
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unsigned int val;
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+ /* PHYA power down */
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
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+
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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@@ -36,6 +40,10 @@ static int mtk_pcs_setup_mode_an(struct
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val |= SGMII_AN_RESTART;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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+ /* Release PHYA power down state
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+ * unknown how much the QPHY needs but it is racy without a sleep
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+ */
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+ usleep_range(50, 100);
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return 0;
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@@ -50,6 +58,9 @@ static int mtk_pcs_setup_mode_force(stru
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{
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unsigned int val;
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+ /* PHYA power down */
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
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+
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regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
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val &= ~RG_PHY_SPEED_MASK;
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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@@ -67,7 +78,10 @@ static int mtk_pcs_setup_mode_force(stru
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val |= SGMII_SPEED_1000;
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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- /* Release PHYA power down state */
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+ /* Release PHYA power down state
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+ * unknown how much the QPHY needs but it is racy without a sleep
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+ */
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+ usleep_range(50, 100);
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return 0;
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@ -0,0 +1,31 @@
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From e4dca7affb8c03438b63bdb5fddefd6ad2431cfd Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Mon, 15 Aug 2022 14:59:29 +0200
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Subject: [PATCH 07/10] net: mtk_sgmii: mtk_pcs_setup_mode_an: don't rely on
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register defaults
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Ensure autonegotiation is enabled.
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_sgmii.c | 5 +++--
|
||||
1 file changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
||||
@@ -32,12 +32,13 @@ static int mtk_pcs_setup_mode_an(struct
|
||||
regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
|
||||
SGMII_LINK_TIMER_DEFAULT);
|
||||
|
||||
+ /* disable remote fault & enable auto neg */
|
||||
regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
|
||||
- val |= SGMII_REMOTE_FAULT_DIS;
|
||||
+ val |= SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN;
|
||||
regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
|
||||
|
||||
regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
|
||||
- val |= SGMII_AN_RESTART;
|
||||
+ val |= SGMII_AN_RESTART | SGMII_AN_ENABLE;
|
||||
regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
|
||||
|
||||
/* Release PHYA power down state
|
@ -0,0 +1,47 @@
|
||||
From 952b64575613d26163a5afa5ff8bfdb57840091b Mon Sep 17 00:00:00 2001
|
||||
From: Alexander Couzens <lynxis@fe80.eu>
|
||||
Date: Mon, 15 Aug 2022 15:00:14 +0200
|
||||
Subject: [PATCH 08/10] net: mtk_sgmii: set the speed according to the phy
|
||||
interface in AN
|
||||
|
||||
The non auto-negotioting code path is setting the correct speed for the
|
||||
interface. Ensure auto-negotiation code path is doing it as well.
|
||||
|
||||
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 +++++++++--
|
||||
1 file changed, 9 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
||||
@@ -21,13 +21,20 @@ static struct mtk_pcs *pcs_to_mtk_pcs(st
|
||||
}
|
||||
|
||||
/* For SGMII interface mode */
|
||||
-static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
|
||||
+static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t interface)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
/* PHYA power down */
|
||||
regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
|
||||
|
||||
+ /* Set SGMII phy speed */
|
||||
+ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
|
||||
+ val &= ~RG_PHY_SPEED_MASK;
|
||||
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
|
||||
+ val |= RG_PHY_SPEED_3_125G;
|
||||
+ regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
|
||||
+
|
||||
/* Setup the link timer and QPHY power up inside SGMIISYS */
|
||||
regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
|
||||
SGMII_LINK_TIMER_DEFAULT);
|
||||
@@ -100,7 +107,7 @@ static int mtk_pcs_config(struct phylink
|
||||
if (interface != PHY_INTERFACE_MODE_SGMII)
|
||||
err = mtk_pcs_setup_mode_force(mpcs, interface);
|
||||
else if (phylink_autoneg_inband(mode))
|
||||
- err = mtk_pcs_setup_mode_an(mpcs);
|
||||
+ err = mtk_pcs_setup_mode_an(mpcs, interface);
|
||||
|
||||
return err;
|
||||
}
|
@ -0,0 +1,22 @@
|
||||
From 06773f19cffd6c9d34dcbc8320169afef5ab60ba Mon Sep 17 00:00:00 2001
|
||||
From: Alexander Couzens <lynxis@fe80.eu>
|
||||
Date: Mon, 15 Aug 2022 13:58:07 +0200
|
||||
Subject: [PATCH 09/10] net: mtk_eth_soc: improve comment
|
||||
|
||||
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_sgmii.c | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
||||
@@ -80,7 +80,8 @@ static int mtk_pcs_setup_mode_force(stru
|
||||
val &= ~SGMII_AN_ENABLE;
|
||||
regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
|
||||
|
||||
- /* Set the speed etc but leave the duplex unchanged */
|
||||
+ /* Set the speed etc but leave the duplex unchanged.
|
||||
+ * The SGMII mode for 2.5gbit is the same as for 1gbit, expect the speed in ANA_RGC3 */
|
||||
regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
|
||||
val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
|
||||
val |= SGMII_SPEED_1000;
|
@ -0,0 +1,23 @@
|
||||
From 95dcd0f223d7cab6e25bc19088016e5eb4ca1804 Mon Sep 17 00:00:00 2001
|
||||
From: Alexander Couzens <lynxis@fe80.eu>
|
||||
Date: Tue, 16 Aug 2022 00:22:11 +0200
|
||||
Subject: [PATCH 10/10] mtk_sgmii: enable PCS polling to allow SFP work
|
||||
|
||||
Currently there is no IRQ handling (even the SGMII supports it).
|
||||
Enable polling to support SFP ports.
|
||||
|
||||
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_sgmii.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
||||
@@ -180,6 +180,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
|
||||
return PTR_ERR(ss->pcs[i].regmap);
|
||||
|
||||
ss->pcs[i].pcs.ops = &mtk_pcs_ops;
|
||||
+ ss->pcs[i].pcs.poll = 1;
|
||||
}
|
||||
|
||||
return 0;
|
Loading…
Reference in New Issue
Block a user