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e504fdae4e
Add pending patches from Alexander 'lynxis' Couzens which are required for RealTek NBase-T PHYs or SFP+ cages to work when connected to the SGMII interface provided by recent MediaTek SoCs [1]. The patches for MT753x fix link speed limitation on CPU ports observed by many users which is due to reset being carried out wrongly [2]. [1]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669488&state=* [2]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669486&state=* Signed-off-by: Daniel Golle <daniel@makrotopia.org>
66 lines
2.1 KiB
Diff
66 lines
2.1 KiB
Diff
From 9daea9b71d060d93d7394ac465b2e5ee0b7e7bca Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Mon, 15 Aug 2022 16:02:01 +0200
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Subject: [PATCH 06/10] net: mtk_sgmii: ensure the SGMII PHY is powered down on
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configuration
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The code expect the PHY to be in power down (which is only true after reset).
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Allow the changes of SGMII parameters more than once.
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---
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 16 +++++++++++++++-
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1 file changed, 15 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -7,6 +7,7 @@
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*
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*/
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+#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/phylink.h>
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@@ -24,6 +25,9 @@ static int mtk_pcs_setup_mode_an(struct
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{
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unsigned int val;
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+ /* PHYA power down */
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
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+
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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@@ -36,6 +40,10 @@ static int mtk_pcs_setup_mode_an(struct
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val |= SGMII_AN_RESTART;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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+ /* Release PHYA power down state
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+ * unknown how much the QPHY needs but it is racy without a sleep
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+ */
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+ usleep_range(50, 100);
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return 0;
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@@ -50,6 +58,9 @@ static int mtk_pcs_setup_mode_force(stru
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{
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unsigned int val;
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+ /* PHYA power down */
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
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+
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regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
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val &= ~RG_PHY_SPEED_MASK;
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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@@ -67,7 +78,10 @@ static int mtk_pcs_setup_mode_force(stru
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val |= SGMII_SPEED_1000;
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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- /* Release PHYA power down state */
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+ /* Release PHYA power down state
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+ * unknown how much the QPHY needs but it is racy without a sleep
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+ */
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+ usleep_range(50, 100);
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return 0;
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