mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 00:11:13 +00:00
cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
36 lines
1.2 KiB
Diff
36 lines
1.2 KiB
Diff
From a1d37fce23d69a51a299b848d0a5700d64e6db4e Mon Sep 17 00:00:00 2001
|
|
From: Alex Marginean <alexandru.marginean@nxp.com>
|
|
Date: Tue, 7 Jan 2020 16:48:05 +0200
|
|
Subject: [PATCH] drivers: net: phylink: in-band AN for USXGMII
|
|
|
|
USXGMII supports passing link information in-band between PHY and MAC PCS,
|
|
add it to the list of protocls that support in-band AN mode.
|
|
|
|
TODO:
|
|
Add 2500baseT, 5GbaseT, 10GbaseT.
|
|
|
|
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
|
---
|
|
drivers/net/phy/phylink.c | 10 ++++++++++
|
|
1 file changed, 10 insertions(+)
|
|
|
|
--- a/drivers/net/phy/phylink.c
|
|
+++ b/drivers/net/phy/phylink.c
|
|
@@ -300,6 +300,16 @@ static int phylink_parse_mode(struct phy
|
|
phylink_set(pl->supported, 2500baseX_Full);
|
|
break;
|
|
|
|
+ case PHY_INTERFACE_MODE_USXGMII:
|
|
+ phylink_set(pl->supported, 10baseT_Half);
|
|
+ phylink_set(pl->supported, 10baseT_Full);
|
|
+ phylink_set(pl->supported, 100baseT_Half);
|
|
+ phylink_set(pl->supported, 100baseT_Full);
|
|
+ phylink_set(pl->supported, 1000baseT_Half);
|
|
+ phylink_set(pl->supported, 1000baseT_Full);
|
|
+ phylink_set(pl->supported, 2500baseX_Full);
|
|
+ break;
|
|
+
|
|
case PHY_INTERFACE_MODE_10GKR:
|
|
phylink_set(pl->supported, 10baseT_Half);
|
|
phylink_set(pl->supported, 10baseT_Full);
|