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4ed209326b
Siflower SF19A2890 is an SoC with: Dual-core MIPS InterAptiv at 800MHz DDR3 controller One Gigabit Ethernet MAC with RGMII and IPv4 HNAT engine Built-in 2x2 11N + 2x2 11AC WiFi radio USB 2.0 OTG I2C/SPI/GPIO and various other peripherals This PR adds support for SF19A2890 EVB with ethernet support. EVB spec: Memory: DDR3 128M Ethernet: RTL8367RB 5-port gigabit switch Flash: 16M NOR Others: MicroUSB OTG, LED x 1, Reset button x1 The built image can be flashed using u-boot recovery. This target is marked as source-only until support for a commercial router board comes. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
652 lines
15 KiB
Plaintext
652 lines
15 KiB
Plaintext
#include <dt-bindings/clock/siflower,sf19a2890-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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/ {
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compatible = "siflower,sf19a2890";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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};
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chosen {
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bootargs = "earlycon";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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wlan24_dsp: wlandsp@1f00000 {
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reg = <0x01f00000 0x200000>;
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};
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wlan5_dsp: wlandsp@2100000 {
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reg = <0x02100000 0x200000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mti,interaptiv";
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reg = <0>;
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clocks = <&clk CLK_MUXDIV_CPU>;
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clock-names = "cpu";
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clock-latency = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "mti,interaptiv";
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reg = <1>;
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clocks = <&clk CLK_MUXDIV_CPU>;
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clock-names = "cpu";
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clock-latency = <0>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "mti,interaptiv";
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reg = <2>;
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clocks = <&clk CLK_MUXDIV_CPU>;
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clock-names = "cpu";
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clock-latency = <0>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "mti,interaptiv";
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reg = <3>;
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clocks = <&clk CLK_MUXDIV_CPU>;
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clock-names = "cpu";
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clock-latency = <0>;
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};
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};
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osc32k: oscillator-32k {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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clock-output-names = "osc32k";
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};
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osc12m: oscillator-12m {
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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#clock-cells = <0>;
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clock-output-names = "osc12m";
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};
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osc40m: oscillator-40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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clock-output-names = "osc40m";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&gic>;
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gmac: ethernet@10800000 {
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compatible = "siflower,sf19a2890-gmac", "snps,dwmac";
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reg = <0x10800000 0x200000>,
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<0x19e04440 0x10>;
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interrupts = <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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clocks = <&gmacclk 0>, <&gmacclk 1>, <&gmacclk 3>, <&gmacclk 2>;
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clock-names = "stmmaceth", "pclk", "ptp_ref", "gmac_byp_ref";
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resets = <&gmacrst 0>;
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reset-names = "stmmaceth";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>, <&mdio_pins>;
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status = "disabled";
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mdio: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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wlan_rf: phy@11c00000{
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compatible = "siflower,sf19a2890-rf";
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reg = <0x11c00000 0x600000>;
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interrupts = <GIC_SHARED 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rfclk 1>, <&rfclk 2>, <&rfclk 3>;
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clock-names = "axi", "boot", "lp";
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resets = <&rfrst 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&wlan_pins>;
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status = "disabled";
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};
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usb: usb@17000000 {
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compatible = "siflower,sf19a2890-usb";
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reg = <0x17000000 0x40000>;
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interrupts = <GIC_SHARED 128 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usbclk 0>;
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clock-names = "otg";
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resets = <&usbrst 0>;
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reset-names = "dwc2";
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dr_mode = "otg";
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phys = <&usb_phy>;
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phy-names = "usb2-phy";
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g-np-tx-fifo-size = <768>;
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status = "disabled";
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};
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i2c: i2c@18100000 {
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compatible = "snps,designware-i2c";
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reg = <0x18100000 0x1000>;
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interrupts = <GIC_SHARED 217 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2cclk 0>;
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clock-names = "ref";
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resets = <&i2crst 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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};
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spi: spi@18202000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x18202000 0x1000>;
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cs-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
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clocks = <&spiclk 1>, <&spiclk 0>;
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clock-names = "sspclk", "apb_pclk";
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interrupts = <GIC_SHARED 225 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&spirst 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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status = "disabled";
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};
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uart0: serial@18300000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x18300000 0x1000>;
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interrupts = <GIC_SHARED 226 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk 3>, <&uartclk 0>;
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clock-names = "uartclk", "apb_pclk";
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resets = <&uartrst 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "disabled";
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};
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uart1: serial@18301000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x18301000 0x1000>;
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interrupts = <GIC_SHARED 227 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk 4>, <&uartclk 1>;
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clock-names = "uartclk", "apb_pclk";
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resets = <&uartrst 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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uart2: serial@18302000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x18302000 0x1000>;
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interrupts = <GIC_SHARED 228 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk 5>, <&uartclk 2>;
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clock-names = "uartclk", "apb_pclk";
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resets = <&uartrst 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "disabled";
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};
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watchdog: watchdog@18700000 {
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compatible = "snps,dw-wdt";
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reg = <0x18700000 0x1000>;
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interrupts = <GIC_SHARED 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&wdtclk 0>;
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resets = <&wdtrst 0>;
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};
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gpio: gpio@19d00000 {
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compatible = "siflower,sf19a2890-gpio";
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reg=<0x19d00000 0x100000>;
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interrupts = <GIC_SHARED 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 249 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gpioclk 0>;
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resets = <&gpiorst 0>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 49>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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clk: clock-controller@19e01000 {
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compatible = "siflower,sf19a2890-clk";
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reg = <0x19e01000 0x800>;
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clocks = <&osc12m>, <&osc40m>;
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clock-names = "osc12m", "osc40m";
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#clock-cells = <1>;
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};
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brom_sysm: syscon@19e02000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x19e02000 0x100>;
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reboot {
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compatible = "syscon-reboot";
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offset = <0x30>;
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value = <0x1>;
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};
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};
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gmacrst: reset-controller@19e04400 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e04400 0x4>;
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#reset-cells = <1>;
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siflower,reset-masks = <0x3>;
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};
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gmacclk: clock-controller@19e04404 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e04404 0xc>;
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clocks = <&clk CLK_MUXDIV_BUS1>, <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_GMAC_BYP_REF>, <&clk CLK_MUXDIV_ETH_TSU>;
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clock-output-names = "gmac", "gmac_pclk", "gmac_byp_ref", "ethtsu";
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#clock-cells = <1>;
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};
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wlan24rst: reset-controller@19e08000 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e08000 0x4>;
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#reset-cells = <1>;
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siflower,reset-masks = <0x7>;
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};
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wlan24clk: clock-controller@19e08004 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e08004 0xc>;
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clocks = <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_WLAN24_PLF>;
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clock-output-names = "wlan24_axis", "wlan24_axim", "wlan24_plf";
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#clock-cells = <1>;
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};
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rfrst: reset-controller@19e08800 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e08800 0x4>;
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#reset-cells = <1>;
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siflower,reset-masks = <0x7>;
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};
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rfclk: clock-controller@19e08804 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e08804 0xc>;
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clocks = <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_CPU>, <&osc12m>, <&osc32k>;
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clock-output-names = "rf_dft", "rf_axis", "rf_boot", "rf_lp";
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#clock-cells = <1>;
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};
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usbrst: reset-controller@19e0c000 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e0c000 0x4>;
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#reset-cells = <1>;
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siflower,reset-masks = <0x7 0x8 0x10>;
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};
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usbclk: clock-controller@19e0c004 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e0c004 0xc>;
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clocks = <&clk CLK_MUXDIV_BUS3>, <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_USBPHY_REF>;
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clock-output-names = "usb", "usb_axim", "usbphy_ref";
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siflower,valid-gates = <0xd>;
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siflower,critical-gates = <0x4>;
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#clock-cells = <1>;
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};
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usb_phy: usb-phy@19e0c040 {
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compatible = "siflower,sf19a2890-usb-phy";
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reg = <0x19e0C040 0x60>;
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clocks = <&usbclk 2>;
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resets = <&usbrst 1>, <&usbrst 2>;
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reset-names = "power_on_rst", "usb_phy_rst";
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#phy-cells = <0>;
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status = "disabled";
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};
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wlan5rst: reset-controller@19e0c400 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e0c400 0x4>;
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#reset-cells = <1>;
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siflower,reset-masks = <0x7>;
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};
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wlan5clk: clock-controller@19e0c404 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e0c404 0xc>;
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clocks = <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_WLAN5_PLF>;
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clock-output-names = "wlan5_axis", "wlan5_axim", "wlan5_plf";
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#clock-cells = <1>;
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};
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i2crst: reset-controller@19e24400 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e24400 0x4>;
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#reset-cells = <1>;
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siflower,num-resets = <1>;
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};
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i2cclk: clock-controller@19e24404 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e24404 0xc>;
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clocks = <&clk CLK_MUXDIV_PBUS>;
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clock-output-names = "i2c0";
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#clock-cells = <1>;
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};
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spirst: reset-controller@19e24800 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e24800 0x4>;
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#reset-cells = <1>;
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siflower,reset-masks = <0x30>;
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};
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spiclk: clock-controller@19e24804 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e24804 0xc>;
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clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>;
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clock-output-names = "spi_apb", "spi_ssp";
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siflower,valid-gates = <0x30>;
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#clock-cells = <1>;
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};
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uartrst: reset-controller@19e24c00 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e24c00 0x4>;
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#reset-cells = <1>;
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siflower,reset-masks = <0x11 0x22 0x44>;
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};
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uartclk: clock-controller@19e24c04 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e24c04 0xc>;
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clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>,
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<&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>;
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clock-output-names = "uart0_apb", "uart1_apb", "uart2_apb",
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"uart0", "uart1","uart2";
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siflower,valid-gates = <0x77>;
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siflower,critical-gates = <0x11>;
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#clock-cells = <1>;
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};
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pwmrst: reset-controller@19e25400 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e25400 0x4>;
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#reset-cells = <1>;
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siflower,num-resets = <1>;
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};
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pwmclk: clock-controller@19e25404 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e25404 0xc>;
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clocks = <&clk CLK_MUXDIV_PBUS>;
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clock-output-names = "pwm";
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#clock-cells = <1>;
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};
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timerrst: reset-controller@19e25800 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e25800 0x4>;
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#reset-cells = <1>;
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siflower,num-resets = <1>;
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};
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timerclk: clock-controller@19e25804 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e25804 0xc>;
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clocks = <&clk CLK_MUXDIV_PBUS>;
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clock-output-names = "timer";
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#clock-cells = <1>;
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};
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wdtrst: reset-controller@19e25c00 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e25c00 0x4>;
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#reset-cells = <1>;
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siflower,num-resets = <1>;
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};
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wdtclk: clock-controller@19e25c04 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e25c04 0xc>;
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clocks = <&clk CLK_MUXDIV_PBUS>;
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clock-output-names = "wdt";
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#clock-cells = <1>;
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};
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gpiorst: reset-controller@19e2b400 {
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compatible = "siflower,sf19a2890-periph-reset";
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reg = <0x19e2b400 0x4>;
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#reset-cells = <1>;
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siflower,num-resets = <1>;
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};
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gpioclk: clock-controller@19e2b404 {
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compatible = "siflower,sf19a2890-periph-clk";
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reg = <0x19e2b404 0xc>;
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clocks = <&clk CLK_MUXDIV_PBUS>;
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clock-output-names = "gpio";
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#clock-cells = <1>;
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};
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pinctrl: pinctrl@19e3fc00 {
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compatible = "siflower,sf19a2890-pinctrl";
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reg = <0x19e3fc00 0x400>;
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jtag_pins: jtag-pins {
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tdo {
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pins = "JTAG_TDO";
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function = "func0";
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bias-disable;
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};
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input-pins {
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pins = "JTAG_TDI", "JTAG_TMS", "JTAG_TCK";
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function = "func0";
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input-enable;
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bias-disable;
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};
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trst {
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pins = "JTAG_RST";
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function = "func0";
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input-enable;
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bias-pull-down;
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};
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};
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spi_pins: spi-pins {
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sck {
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pins = "SPI_CLK";
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function = "func0";
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bias-disable;
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};
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|
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mosi {
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pins = "SPI_TXD";
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function = "func0";
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bias-pull-down;
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};
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miso {
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pins = "SPI_RXD";
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function = "func0";
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input-enable;
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bias-pull-down;
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};
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cs {
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pins = "SPI_CSN";
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bias-pull-up;
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};
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};
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|
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uart0_pins: uart0-pins {
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tx {
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pins = "UART_TX";
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function = "func0";
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bias-pull-up;
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};
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|
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rx {
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pins = "UART_RX";
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function = "func0";
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input-enable;
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bias-pull-up;
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};
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};
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|
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uart0_rtscts: uart0-rtscts-pins {
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cts {
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pins = "I2C_DAT";
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function = "func0";
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input-enable;
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|
bias-pull-up;
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|
};
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|
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rts {
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|
pins = "I2C_CLK";
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|
function = "func0";
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|
bias-pull-up;
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|
};
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};
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|
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uart1_pins: uart1-pins {
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|
tx {
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|
pins = "JATG_TDO";
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|
function = "func1";
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|
bias-pull-up;
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|
};
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|
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rx {
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|
pins = "JATG_TDI";
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|
function = "func1";
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|
input-enable;
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|
bias-pull-up;
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|
};
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|
};
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|
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uart1_rtscts: uart1-rtscts-pins {
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|
cts {
|
|
pins = "JTAG_TMS";
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|
function = "func1";
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|
input-enable;
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|
bias-pull-up;
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|
};
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|
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rts {
|
|
pins = "JTAG_TCK";
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|
function = "func1";
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|
bias-pull-up;
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|
};
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|
};
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|
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uart2_pins: uart2-pins {
|
|
tx {
|
|
pins = "I2C_DAT";
|
|
function = "func1";
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|
bias-pull-up;
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|
};
|
|
|
|
rx {
|
|
pins = "I2C_CLK";
|
|
function = "func1";
|
|
input-enable;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
rgmii_pins: rgmii-pins {
|
|
tx-pins {
|
|
pins = "RGMII_TXCLK", "RGMII_TXD0",
|
|
"RGMII_TXD1", "RGMII_TXD2",
|
|
"RGMII_TXD3", "RGMII_TXCTL";
|
|
function = "func0";
|
|
bias-disable;
|
|
};
|
|
|
|
rx-pins {
|
|
pins = "RGMII_RXCLK", "RGMII_RXD0",
|
|
"RGMII_RXD1", "RGMII_RXD2",
|
|
"RGMII_RXD3", "RGMII_RXCTL";
|
|
function = "func0";
|
|
input-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
mdio_pins: mdio-pins {
|
|
pins {
|
|
pins = "RGMII_MDC", "RGMII_MDIO";
|
|
function = "func0";
|
|
input-enable;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
wlan_pins: wlan-pins {
|
|
pins {
|
|
pins = "HB0_PA_EN", "HB0_LNA_EN",
|
|
"HB0_SW_CTRL0", "HB0_SW_CTRL1",
|
|
"HB1_PA_EN", "HB1_LNA_EN",
|
|
"HB1_SW_CTRL0", "HB1_SW_CTRL1",
|
|
"LB0_PA_EN", "LB0_LNA_EN",
|
|
"LB0_SW_CTRL0", "LB0_SW_CTRL1",
|
|
"LB1_PA_EN", "LB1_LNA_EN",
|
|
"LB1_SW_CTRL0", "LB1_SW_CTRL1";
|
|
function = "func0";
|
|
};
|
|
};
|
|
|
|
|
|
i2c0_pins: i2c0-pins {
|
|
pins {
|
|
pins = "I2C_CLK", "I2C_DAT";
|
|
function = "func2";
|
|
input-enable;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@1bdc0000 {
|
|
compatible = "mti,gic";
|
|
reg = <0x1bdc0000 0x20000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
mti,reserved-ipi-vectors = <0 8>;
|
|
|
|
timer {
|
|
compatible = "mti,gic-timer";
|
|
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
|
clocks = <&clk CLK_MUXDIV_CPU>;
|
|
};
|
|
};
|
|
};
|
|
};
|