openwrt/target/linux/siflower/dts/sf19a2890.dtsi

#include <dt-bindings/clock/siflower,sf19a2890-clk.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/mips-gic.h>

/ {
	compatible = "siflower,sf19a2890";
	#address-cells = <1>;
	#size-cells = <1>;


	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	chosen {
		bootargs = "earlycon";
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		wlan24_dsp: wlandsp@1f00000 {
			reg = <0x01f00000 0x200000>;
		};

		wlan5_dsp: wlandsp@2100000 {
			reg = <0x02100000 0x200000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "mti,interaptiv";
			reg = <0>;
			clocks = <&clk CLK_MUXDIV_CPU>;
			clock-names = "cpu";
			clock-latency = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "mti,interaptiv";
			reg = <1>;
			clocks = <&clk CLK_MUXDIV_CPU>;
			clock-names = "cpu";
			clock-latency = <0>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "mti,interaptiv";
			reg = <2>;
			clocks = <&clk CLK_MUXDIV_CPU>;
			clock-names = "cpu";
			clock-latency = <0>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "mti,interaptiv";
			reg = <3>;
			clocks = <&clk CLK_MUXDIV_CPU>;
			clock-names = "cpu";
			clock-latency = <0>;
		};
	};

	osc32k: oscillator-32k {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		#clock-cells = <0>;
		clock-output-names = "osc32k";
	};

	osc12m: oscillator-12m {
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
		#clock-cells = <0>;
		clock-output-names = "osc12m";
	};

	osc40m: oscillator-40m {
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
		#clock-cells = <0>;
		clock-output-names = "osc40m";
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = <&gic>;

		gmac: ethernet@10800000 {
			compatible = "siflower,sf19a2890-gmac", "snps,dwmac";
			reg = <0x10800000 0x200000>,
				<0x19e04440 0x10>;
			interrupts = <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			clocks = <&gmacclk 0>, <&gmacclk 1>, <&gmacclk 3>, <&gmacclk 2>;
			clock-names = "stmmaceth", "pclk", "ptp_ref", "gmac_byp_ref";
			resets = <&gmacrst 0>;
			reset-names = "stmmaceth";
			pinctrl-names = "default";
			pinctrl-0 = <&rgmii_pins>, <&mdio_pins>;
			status = "disabled";

			mdio: mdio {
				compatible = "snps,dwmac-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		wlan_rf: phy@11c00000{
			compatible = "siflower,sf19a2890-rf";
			reg = <0x11c00000 0x600000>;
			interrupts = <GIC_SHARED 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rfclk 1>, <&rfclk 2>, <&rfclk 3>;
			clock-names = "axi", "boot", "lp";
			resets = <&rfrst 0>;
			pinctrl-names = "default";
			pinctrl-0 = <&wlan_pins>;
			status = "disabled";
		};

		usb: usb@17000000 {
			compatible = "siflower,sf19a2890-usb";
			reg = <0x17000000 0x40000>;
			interrupts = <GIC_SHARED 128 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usbclk 0>;
			clock-names = "otg";
			resets = <&usbrst 0>;
			reset-names = "dwc2";
			dr_mode = "otg";
			phys = <&usb_phy>;
			phy-names = "usb2-phy";
			g-np-tx-fifo-size = <768>;
			status = "disabled";
		};

		i2c: i2c@18100000 {
			compatible = "snps,designware-i2c";
			reg = <0x18100000 0x1000>;
			interrupts = <GIC_SHARED 217 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&i2cclk 0>;
			clock-names = "ref";
			resets = <&i2crst 0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pins>;
		};

		spi: spi@18202000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x18202000 0x1000>;
			cs-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
			clocks = <&spiclk 1>, <&spiclk 0>;
			clock-names = "sspclk", "apb_pclk";
			interrupts = <GIC_SHARED 225 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&spirst 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi_pins>;
			status = "disabled";
		};

		uart0: serial@18300000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x18300000 0x1000>;
			interrupts = <GIC_SHARED 226 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk 3>, <&uartclk 0>;
			clock-names = "uartclk", "apb_pclk";
			resets = <&uartrst 0>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pins>;
			status = "disabled";
		};

		uart1: serial@18301000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x18301000 0x1000>;
			interrupts = <GIC_SHARED 227 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk 4>, <&uartclk 1>;
			clock-names = "uartclk", "apb_pclk";
			resets = <&uartrst 1>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_pins>;
			status = "disabled";
		};

		uart2: serial@18302000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x18302000 0x1000>;
			interrupts = <GIC_SHARED 228 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk 5>, <&uartclk 2>;
			clock-names = "uartclk", "apb_pclk";
			resets = <&uartrst 2>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_pins>;
			status = "disabled";
		};

		watchdog: watchdog@18700000 {
			compatible = "snps,dw-wdt";
			reg = <0x18700000 0x1000>;
			interrupts = <GIC_SHARED 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&wdtclk 0>;
			resets = <&wdtrst 0>;
		};

		gpio: gpio@19d00000 {
			compatible = "siflower,sf19a2890-gpio";
			reg=<0x19d00000 0x100000>;
			interrupts = <GIC_SHARED 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SHARED 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SHARED 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SHARED 249 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gpioclk 0>;
			resets = <&gpiorst 0>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 49>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		clk: clock-controller@19e01000 {
			compatible = "siflower,sf19a2890-clk";
			reg = <0x19e01000 0x800>;
			clocks = <&osc12m>, <&osc40m>;
			clock-names = "osc12m", "osc40m";
			#clock-cells = <1>;
		};

		brom_sysm: syscon@19e02000 {
			compatible = "syscon", "simple-mfd";
			reg = <0x19e02000 0x100>;

			reboot {
				compatible = "syscon-reboot";
				offset = <0x30>;
				value = <0x1>;
			};
		};

		gmacrst: reset-controller@19e04400 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e04400 0x4>;
			#reset-cells = <1>;
			siflower,reset-masks = <0x3>;
		};

		gmacclk: clock-controller@19e04404 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e04404 0xc>;
			clocks = <&clk CLK_MUXDIV_BUS1>, <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_GMAC_BYP_REF>, <&clk CLK_MUXDIV_ETH_TSU>;
			clock-output-names = "gmac", "gmac_pclk", "gmac_byp_ref", "ethtsu";
			#clock-cells = <1>;
		};

		wlan24rst: reset-controller@19e08000 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e08000 0x4>;
			#reset-cells = <1>;
			siflower,reset-masks = <0x7>;
		};

		wlan24clk: clock-controller@19e08004 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e08004 0xc>;
			clocks = <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_WLAN24_PLF>;
			clock-output-names = "wlan24_axis", "wlan24_axim", "wlan24_plf";
			#clock-cells = <1>;
		};

		rfrst: reset-controller@19e08800 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e08800 0x4>;
			#reset-cells = <1>;
			siflower,reset-masks = <0x7>;
		};

		rfclk: clock-controller@19e08804 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e08804 0xc>;
			clocks = <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_CPU>, <&osc12m>, <&osc32k>;
			clock-output-names = "rf_dft", "rf_axis", "rf_boot", "rf_lp";
			#clock-cells = <1>;
		};

		usbrst: reset-controller@19e0c000 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e0c000 0x4>;
			#reset-cells = <1>;
			siflower,reset-masks = <0x7 0x8 0x10>;
		};

		usbclk: clock-controller@19e0c004 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e0c004 0xc>;
			clocks = <&clk CLK_MUXDIV_BUS3>, <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_USBPHY_REF>;
			clock-output-names = "usb", "usb_axim", "usbphy_ref";
			siflower,valid-gates = <0xd>;
			siflower,critical-gates = <0x4>;
			#clock-cells = <1>;
		};

		usb_phy: usb-phy@19e0c040 {
			compatible = "siflower,sf19a2890-usb-phy";
			reg = <0x19e0C040 0x60>;
			clocks = <&usbclk 2>;
			resets = <&usbrst 1>, <&usbrst 2>;
			reset-names = "power_on_rst", "usb_phy_rst";
			#phy-cells = <0>;
			status = "disabled";
		};

		wlan5rst: reset-controller@19e0c400 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e0c400 0x4>;
			#reset-cells = <1>;
			siflower,reset-masks = <0x7>;
		};

		wlan5clk: clock-controller@19e0c404 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e0c404 0xc>;
			clocks = <&clk CLK_MUXDIV_CPU>, <&clk CLK_MUXDIV_BUS2>, <&clk CLK_MUXDIV_WLAN5_PLF>;
			clock-output-names = "wlan5_axis", "wlan5_axim", "wlan5_plf";
			#clock-cells = <1>;
		};

		i2crst: reset-controller@19e24400 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e24400 0x4>;
			#reset-cells = <1>;
			siflower,num-resets = <1>;
		};

		i2cclk: clock-controller@19e24404 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e24404 0xc>;
			clocks = <&clk CLK_MUXDIV_PBUS>;
			clock-output-names = "i2c0";
			#clock-cells = <1>;
		};

		spirst: reset-controller@19e24800 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e24800 0x4>;
			#reset-cells = <1>;
			siflower,reset-masks = <0x30>;
		};

		spiclk: clock-controller@19e24804 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e24804 0xc>;
			clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>;
			clock-output-names = "spi_apb", "spi_ssp";
			siflower,valid-gates = <0x30>;
			#clock-cells = <1>;
		};

		uartrst: reset-controller@19e24c00 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e24c00 0x4>;
			#reset-cells = <1>;
			siflower,reset-masks = <0x11 0x22 0x44>;
		};

		uartclk: clock-controller@19e24c04 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e24c04 0xc>;
			clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>,
				 <&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>;
			clock-output-names = "uart0_apb", "uart1_apb", "uart2_apb",
					     "uart0", "uart1","uart2";
			siflower,valid-gates = <0x77>;
			siflower,critical-gates = <0x11>;
			#clock-cells = <1>;
		};

		pwmrst: reset-controller@19e25400 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e25400 0x4>;
			#reset-cells = <1>;
			siflower,num-resets = <1>;
		};

		pwmclk: clock-controller@19e25404 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e25404 0xc>;
			clocks = <&clk CLK_MUXDIV_PBUS>;
			clock-output-names = "pwm";
			#clock-cells = <1>;
		};

		timerrst: reset-controller@19e25800 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e25800 0x4>;
			#reset-cells = <1>;
			siflower,num-resets = <1>;
		};

		timerclk: clock-controller@19e25804 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e25804 0xc>;
			clocks = <&clk CLK_MUXDIV_PBUS>;
			clock-output-names = "timer";
			#clock-cells = <1>;
		};

		wdtrst: reset-controller@19e25c00 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e25c00 0x4>;
			#reset-cells = <1>;
			siflower,num-resets = <1>;
		};

		wdtclk: clock-controller@19e25c04 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e25c04 0xc>;
			clocks = <&clk CLK_MUXDIV_PBUS>;
			clock-output-names = "wdt";
			#clock-cells = <1>;
		};

		gpiorst: reset-controller@19e2b400 {
			compatible = "siflower,sf19a2890-periph-reset";
			reg = <0x19e2b400 0x4>;
			#reset-cells = <1>;
			siflower,num-resets = <1>;
		};

		gpioclk: clock-controller@19e2b404 {
			compatible = "siflower,sf19a2890-periph-clk";
			reg = <0x19e2b404 0xc>;
			clocks = <&clk CLK_MUXDIV_PBUS>;
			clock-output-names = "gpio";
			#clock-cells = <1>;
		};

		pinctrl: pinctrl@19e3fc00 {
			compatible = "siflower,sf19a2890-pinctrl";
			reg = <0x19e3fc00 0x400>;

			jtag_pins: jtag-pins {
				tdo {
					pins = "JTAG_TDO";
					function = "func0";
					bias-disable;
				};

				input-pins {
					pins = "JTAG_TDI", "JTAG_TMS", "JTAG_TCK";
					function = "func0";
					input-enable;
					bias-disable;
				};

				trst {
					pins = "JTAG_RST";
					function = "func0";
					input-enable;
					bias-pull-down;
				};
			};

			spi_pins: spi-pins {
				sck {
					pins = "SPI_CLK";
					function = "func0";
					bias-disable;
				};

				mosi {
					pins = "SPI_TXD";
					function = "func0";
					bias-pull-down;
				};

				miso {
					pins = "SPI_RXD";
					function = "func0";
					input-enable;
					bias-pull-down;
				};

				cs {
					pins = "SPI_CSN";
					bias-pull-up;
				};
			};

			uart0_pins: uart0-pins {
				tx {
					pins = "UART_TX";
					function = "func0";
					bias-pull-up;
				};

				rx {
					pins = "UART_RX";
					function = "func0";
					input-enable;
					bias-pull-up;
				};
			};

			uart0_rtscts: uart0-rtscts-pins {
				cts {
					pins = "I2C_DAT";
					function = "func0";
					input-enable;
					bias-pull-up;
				};

				rts {
					pins = "I2C_CLK";
					function = "func0";
					bias-pull-up;
				};
			};

			uart1_pins: uart1-pins {
				tx {
					pins = "JATG_TDO";
					function = "func1";
					bias-pull-up;
				};

				rx {
					pins = "JATG_TDI";
					function = "func1";
					input-enable;
					bias-pull-up;
				};
			};

			uart1_rtscts: uart1-rtscts-pins {
				cts {
					pins = "JTAG_TMS";
					function = "func1";
					input-enable;
					bias-pull-up;
				};

				rts {
					pins = "JTAG_TCK";
					function = "func1";
					bias-pull-up;
				};
			};

			uart2_pins: uart2-pins {
				tx {
					pins = "I2C_DAT";
					function = "func1";
					bias-pull-up;
				};

				rx {
					pins = "I2C_CLK";
					function = "func1";
					input-enable;
					bias-pull-up;
				};
			};

			rgmii_pins: rgmii-pins {
				tx-pins {
					pins =  "RGMII_TXCLK", "RGMII_TXD0",
						"RGMII_TXD1", "RGMII_TXD2",
						"RGMII_TXD3", "RGMII_TXCTL";
					function = "func0";
					bias-disable;
				};

				rx-pins {
					pins = "RGMII_RXCLK", "RGMII_RXD0",
						"RGMII_RXD1", "RGMII_RXD2",
						"RGMII_RXD3", "RGMII_RXCTL";
					function = "func0";
					input-enable;
					bias-disable;
				};
			};

			mdio_pins: mdio-pins {
				pins {
					pins = "RGMII_MDC", "RGMII_MDIO";
					function = "func0";
					input-enable;
					bias-pull-up;
				};
			};

			wlan_pins: wlan-pins {
				pins {
					pins = "HB0_PA_EN", "HB0_LNA_EN",
						"HB0_SW_CTRL0", "HB0_SW_CTRL1",
						"HB1_PA_EN", "HB1_LNA_EN",
						"HB1_SW_CTRL0", "HB1_SW_CTRL1",
						"LB0_PA_EN", "LB0_LNA_EN",
						"LB0_SW_CTRL0", "LB0_SW_CTRL1",
						"LB1_PA_EN", "LB1_LNA_EN",
						"LB1_SW_CTRL0", "LB1_SW_CTRL1";
					function = "func0";
				};
			};


			i2c0_pins: i2c0-pins {
				pins {
					pins = "I2C_CLK", "I2C_DAT";
					function = "func2";
					input-enable;
					bias-pull-up;
				};
			};
		};

		gic: interrupt-controller@1bdc0000 {
			compatible = "mti,gic";
			reg = <0x1bdc0000 0x20000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			mti,reserved-ipi-vectors = <0 8>;

			timer {
				compatible = "mti,gic-timer";
				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
				clocks = <&clk CLK_MUXDIV_CPU>;
			};
		};
	};
};