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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
56 lines
1.7 KiB
Diff
56 lines
1.7 KiB
Diff
From 6f49bc0ee169c90b5c26a1e3d27a4728142f0ddb Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:48:34 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY
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IPQ8074 comes in 2 silicon versions:
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* v1 with 2x Gen2 PCIe ports and QMP PHY-s
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* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
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v2 is the final and production version that is actually supported by the
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kernel, however it looks like PCIe related nodes were added for the v1 SoC.
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Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
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by fixing the Gen3 QMP PHY node first.
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Change the compatible to the Gen3 QMP PHY, correct the register space start
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and size, add the missing misc PCS register space.
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Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
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1 file changed, 8 insertions(+), 7 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -232,9 +232,9 @@
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status = "disabled";
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};
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- pcie_qmp0: phy@86000 {
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- compatible = "qcom,ipq8074-qmp-pcie-phy";
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- reg = <0x00086000 0x1c4>;
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+ pcie_qmp0: phy@84000 {
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+ compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
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+ reg = <0x00084000 0x1bc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@@ -248,10 +248,11 @@
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"common";
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status = "disabled";
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- pcie_phy0: phy@86200 {
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- reg = <0x86200 0x16c>,
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- <0x86400 0x200>,
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- <0x86800 0x4f4>;
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+ pcie_phy0: phy@84200 {
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+ reg = <0x84200 0x16c>,
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+ <0x84400 0x200>,
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+ <0x84800 0x1f0>,
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+ <0x84c00 0xf4>;
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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