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56 lines
1.7 KiB
Diff
56 lines
1.7 KiB
Diff
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From 6f49bc0ee169c90b5c26a1e3d27a4728142f0ddb Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:48:34 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY
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IPQ8074 comes in 2 silicon versions:
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* v1 with 2x Gen2 PCIe ports and QMP PHY-s
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* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
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v2 is the final and production version that is actually supported by the
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kernel, however it looks like PCIe related nodes were added for the v1 SoC.
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Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
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by fixing the Gen3 QMP PHY node first.
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Change the compatible to the Gen3 QMP PHY, correct the register space start
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and size, add the missing misc PCS register space.
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Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
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1 file changed, 8 insertions(+), 7 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -232,9 +232,9 @@
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status = "disabled";
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};
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- pcie_qmp0: phy@86000 {
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- compatible = "qcom,ipq8074-qmp-pcie-phy";
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- reg = <0x00086000 0x1c4>;
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+ pcie_qmp0: phy@84000 {
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+ compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
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+ reg = <0x00084000 0x1bc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@@ -248,10 +248,11 @@
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"common";
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status = "disabled";
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- pcie_phy0: phy@86200 {
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- reg = <0x86200 0x16c>,
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- <0x86400 0x200>,
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- <0x86800 0x4f4>;
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+ pcie_phy0: phy@84200 {
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+ reg = <0x84200 0x16c>,
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+ <0x84400 0x200>,
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+ <0x84800 0x1f0>,
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+ <0x84c00 0xf4>;
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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