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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
62 lines
2.0 KiB
Diff
62 lines
2.0 KiB
Diff
From 6f39b05b13e7be39919fd8d235bb0e63ecabf190 Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Tue, 5 Apr 2022 08:34:43 +0200
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Subject: [PATCH] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema
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The DT schema expects dma channels in tx-rx order. No functional
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change.
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
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1 file changed, 8 insertions(+), 8 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -471,8 +471,8 @@
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <400000>;
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- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
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- dma-names = "rx", "tx";
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+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
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+ dma-names = "tx", "rx";
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pinctrl-0 = <&i2c_0_pins>;
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pinctrl-names = "default";
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status = "disabled";
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@@ -488,8 +488,8 @@
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <100000>;
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- dmas = <&blsp_dma 17>, <&blsp_dma 16>;
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- dma-names = "rx", "tx";
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+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
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+ dma-names = "tx", "rx";
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status = "disabled";
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};
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@@ -503,8 +503,8 @@
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<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <400000>;
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- dmas = <&blsp_dma 21>, <&blsp_dma 20>;
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- dma-names = "rx", "tx";
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+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
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+ dma-names = "tx", "rx";
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status = "disabled";
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};
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@@ -518,8 +518,8 @@
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<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <100000>;
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- dmas = <&blsp_dma 23>, <&blsp_dma 22>;
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- dma-names = "rx", "tx";
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+ dmas = <&blsp_dma 22>, <&blsp_dma 23>;
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+ dma-names = "tx", "rx";
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status = "disabled";
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};
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