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62 lines
2.0 KiB
Diff
62 lines
2.0 KiB
Diff
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From 6f39b05b13e7be39919fd8d235bb0e63ecabf190 Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Tue, 5 Apr 2022 08:34:43 +0200
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Subject: [PATCH] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema
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The DT schema expects dma channels in tx-rx order. No functional
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change.
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
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1 file changed, 8 insertions(+), 8 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -471,8 +471,8 @@
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <400000>;
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- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
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- dma-names = "rx", "tx";
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+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
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+ dma-names = "tx", "rx";
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pinctrl-0 = <&i2c_0_pins>;
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pinctrl-names = "default";
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status = "disabled";
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@@ -488,8 +488,8 @@
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <100000>;
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- dmas = <&blsp_dma 17>, <&blsp_dma 16>;
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- dma-names = "rx", "tx";
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+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
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+ dma-names = "tx", "rx";
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status = "disabled";
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};
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@@ -503,8 +503,8 @@
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<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <400000>;
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- dmas = <&blsp_dma 21>, <&blsp_dma 20>;
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- dma-names = "rx", "tx";
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+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
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+ dma-names = "tx", "rx";
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status = "disabled";
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};
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@@ -518,8 +518,8 @@
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<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <100000>;
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- dmas = <&blsp_dma 23>, <&blsp_dma 22>;
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- dma-names = "rx", "tx";
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+ dmas = <&blsp_dma 22>, <&blsp_dma 23>;
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+ dma-names = "tx", "rx";
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status = "disabled";
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};
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