mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 15:02:32 +00:00
cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
60 lines
2.3 KiB
Diff
60 lines
2.3 KiB
Diff
From 060265cd3cec354804c0c944e42de83cec9f2f2a Mon Sep 17 00:00:00 2001
|
|
From: Mihai Serban <mihai.serban@nxp.com>
|
|
Date: Fri, 21 Apr 2017 15:57:58 +0300
|
|
Subject: [PATCH] MLK-14847: Revert "ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI
|
|
master mode"
|
|
|
|
This reverts commit c768ed336bba ("ASoC: fsl-sai: set xCR4/xCR5/xMR for
|
|
SAI master mode")
|
|
|
|
This change was already introduced by commit 51659ca069ce ("ASoC: fsl-sai:
|
|
set xCR4/xCR5/xMR for SAI master mode") from upstream.
|
|
|
|
Manually adjust the code to match the changes introduced by subsequent
|
|
commit b2936555bb38 ("MLK-13609: ASoC: fsl_sai: fix for synchronize mode")
|
|
by removing updates to FSL_SAI_TMR/FSL_SAI_RMR registers.
|
|
|
|
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
|
|
---
|
|
sound/soc/fsl/fsl_sai.c | 29 -----------------------------
|
|
1 file changed, 29 deletions(-)
|
|
|
|
--- a/sound/soc/fsl/fsl_sai.c
|
|
+++ b/sound/soc/fsl/fsl_sai.c
|
|
@@ -507,35 +507,6 @@ static int fsl_sai_hw_params(struct snd_
|
|
regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
|
|
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
|
|
FSL_SAI_CR5_FBT_MASK, val_cr5);
|
|
- regmap_write(sai->regmap, FSL_SAI_TMR,
|
|
- ~0UL - ((1 << channels) - 1));
|
|
- } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
|
|
- regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
|
|
- FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
|
|
- val_cr4);
|
|
- regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
|
|
- FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
|
|
- FSL_SAI_CR5_FBT_MASK, val_cr5);
|
|
- regmap_write(sai->regmap, FSL_SAI_RMR,
|
|
- ~0UL - ((1 << channels) - 1));
|
|
- }
|
|
- }
|
|
-
|
|
- /*
|
|
- * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
|
|
- * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
|
|
- * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
|
|
- * error.
|
|
- */
|
|
-
|
|
- if (!sai->slave_mode[tx]) {
|
|
- if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
|
|
- regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
|
|
- FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
|
|
- val_cr4);
|
|
- regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
|
|
- FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
|
|
- FSL_SAI_CR5_FBT_MASK, val_cr5);
|
|
} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
|
|
regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
|
|
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
|