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e4ce3109f2
The node pinctrl0 is already set up in the SOC DTSI files, but defined again as member of pinctrl in most of the device DTS(I) files. This patch removes this redundancy for the entire ramips target. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
146 lines
2.4 KiB
Plaintext
146 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "xiaomi,mir3g-v2", "mediatek,mt7621-soc";
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model = "Xiaomi Mi Router 3G v2";
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aliases {
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led-boot = &led_status_yellow;
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led-failsafe = &led_status_yellow;
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led-running = &led_status_blue;
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led-upgrade = &led_status_yellow;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led_status_blue: status_blue {
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label = "mir3gv2:blue:status";
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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};
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led_status_yellow: status_yellow {
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label = "mir3gv2:yellow:status";
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gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <80000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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partition@40000 {
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label = "Bdata";
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reg = <0x40000 0x10000>;
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read-only;
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};
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factory: partition@50000 {
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label = "factory";
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reg = <0x50000 0x10000>;
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read-only;
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};
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partition@60000 {
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label = "crash";
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reg = <0x60000 0x10000>;
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read-only;
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};
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partition@70000 {
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label = "cfg_bak";
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reg = <0x70000 0x10000>;
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read-only;
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};
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partition@80000 {
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label = "overlay";
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reg = <0x80000 0x100000>;
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read-only;
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};
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firmware: partition@180000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x180000 0xe80000>;
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};
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "pci14c3,7662";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&pcie1 {
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wifi@0,0 {
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compatible = "pci14c3,7603";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x0000>;
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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ðernet {
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mtd-mac-address = <&factory 0xe000>;
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mediatek,portmap = "lllwl";
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};
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&state_default {
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gpio {
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ralink,group = "jtag", "uart2", "uart3", "wdt";
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ralink,function = "gpio";
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};
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};
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